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Decoding Bit Fields with the JRMK Instruction National Semiconductor Application Brief 34 Michael Allen The JRMK (Jump relative with Rotate and Mask on source register) instruction is designed to decode specific bit fields imbedded in any BCP register quickly and efficiently. Since the transceiver is mapped into the CPU register space, JRMK is a particularly powerful method of decoding the received protocol command, data, and address fields. The decode is accomplished by implementing a jump table in instruction memory. JRMK is used to select a unique table entry by adding an encoded bit field to the current program counter value. JRMK unconditionally transfers program control to a signed offset from the current value of the PC (program counter) + 1. The offset is found by rotating a specific bit field in any register through the CPU barrel shifter and zeroing (masking) any bits in the most significant positions that are not part of this bit field. The least significant bit is always set to 0, allowing compact jump tables to be constructed where each table entry is separated by at least one address. Each table entry can therefore contain any program control instruction, including the 2 word long jumps. This also limits the relative jump range to -128, + 126. The JRMK instruction has 4 fields, as seen in Figure 1. Five bits are dedicated to the source register operand, therefore any of the 32 CPU register addresses can be specified. The rotate field is 3 bits long, allowing the contents of the source register to be rotated (right) from 0 to 7 bits. The 3 bit mask field specifies the number of bits to be zeroed (not including the least significant bit), starting from the msb location. Since the least significant bit is always masked off, the bit field is effectively limited to 7 bits, allowing a maximum table size of 128 entries (-64, +64). The remaining 5 bits are dedicated to the opcode. 15 10 7 4 0 opcode I mask I rotate I source reg I FIGURE 1. JRMK Instruction This instruction does not modify the contents of the source register. Even if the Receive/Transmit Register IRTRl is sourced, the same data will still be present at the output of the receive FIFO following the JRMK. JRMK is a 4 T-state instruction, where a T-state is defined as the period of the CPU clock. A T-state is 50 ns at the maximum rated frequency of operation, therefore the JRMK can execute in as little as 200 ns. This execution time is extended by a slower clock or use of additional instruction wait states. The following example demonstrates the power of the JRMK instruction in processing the encoded address field of the 3299 Terminal Multiplexer protocol. The receiver passes the 3299 address frame to the CPU as the 6 most significant bits in the I RTR l. Only the 3 least significant bits of this 6 bit frame form the encoded address, therefore up to 8 devices can be addressed by the cluster controller. Figure 2 reveals how the Signed offset is formed from the received 3299 address field. The field is rotated 1 bit and the 4 most significant bits of the result will be masked to O. The table will thus have 8 entries starting at the next address after the JRMK instruction. I x x I x I A2 I A1 I AO I x I x I Example 3299 data in receive FIFO (sourced through RTR) I x x I x I x I A2 I A1 I AO x I Location of address field after barrel shifter 0 0 I 0 I 0 I A2 I A1 I AO 0 Resulting offset added to program counter FIGURE 2. Offset Formed by JRMK Rotate and Mask Operations As an example of a real application for this instruction, assume the BCP is designed into a 3299 Terminal Multiplexer emulator product for personal computers. All 8 of the device addresses are supported by the BCP, therefore each of the jump table entries will be a long jump to a control routine for that particular device. Figure 3 represents one way of coding the address frame handling subroutine, using the Hilevel BCP assembler mnemonics. The routine assumes it was called because the Data Available flag was asserted. The error and device control handling routines are not shown, nor is the code at the WRAP label. The addresses assigned to these handlers are chosen arbitrarily. The table entry size can be easily extended to more than 2 addresses by moving the data to a general purpose register and then masking enough bits to allow the bit field to be rotated to a more significant location by the JRMK instruction. Remember, however, that the offset is signed and if the most significant bit is allowed to take on a value of 1 the jump will be negative, requiring the JRMK instruction to be located in the middle of the table. The primary design goal of the BCP was to provide the highest performance solution for coax and twinax communication systems. I n this application, one of the primary functions of the CPU is to process information from the transceiver as fast as possible. The JRMK instruction exemplifies the optimization of the instruction set and architecture for this function. 2-181
.... C") III • cc ;------< 3299 device address decode >----- ;this routine decodes the 3299 protocol device address field ;located in RTR(2-4). It is assumed that the Data Available flag ;or interrupt caused program control to transfer to this ;routine. The error and device handling routines are not shown. OFFC AE08 EXX MA,AB,NAI ;select main A, alt B banks OFFD DD20 JMPF S,RERR,ERRHDLR ;if error, go to error handler OFFE 8DE4 JMPB RTR,S,B7,WRAP ;i1' msb set, wrap data back OFFF 105D 1000 8424 JRMK RTR,ROTl,MSK4 1001 CEOO LJMP ADDR.O ;jump to device 0 handler 1002 2000 1003 CEOO LJMP ADDR.l ;jump to device 1 handler 1004 2050 1005 CEOO LJMP ADDR.2 ;jump to device 2 handler 1006 2100 1007 CEOO LJMP ADDR.3 ;jump to device 3 handler 1008 2150 1009 CEOO LJMP ADDR.4 ;jump to device 4 handler 100A 2200 100B CEOO LJMP ADDR.5 ;jump to device 5 handler 100C 2250 100D CEOO LJMP ADDR.6 ;jump to device 6 handler 100E 2300 100F CEOO LJMP ADDR.7 ;jump to device 7 handler 1010 2350 • • • 1011 AFDO RET EI,RF ;return, restore flags, set GIE ;------< end of routine >------ FIGURE 3. JRMK Code 2·182
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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PAL20LB Decode and DMA Interface Lo
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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An EPROM implementation was selecte
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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3.0 AC Electrical Characteristics T
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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#3/30/B7••••• D2APPS.ASM
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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6.0 Connection Diagrams Dual-In-Lln
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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