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4.0 Timing Waveforms (Continued) Receiver Timing •• u~' SAIIPLECLk ---------------------,U I LJ .CL .. -------~-II_ ... D (REC!~~ \""_ST_._.T_C ....___ D .. ~T_._"_TS_I._-_I} ___ SAMPLE CLK .---~~--~\TI---r---r--rl--,----r~ INTERRUPT (DATA RlADY OR RCVREARI _____________________...I -l (IIEAII.Et ~m---------------------------------------~ ..::;:-----------------------~ IN0lE2, TL/C/9329-7 OUT~~~trT\ \ START I INTERRUPT ITHAE) --------..1'I.s~ Transmitter Timing DATA 15-81 ~ST~A·~tf~------- ~~TI-J ~ _~"R~'SI--'I -I'"R j.: I --j r\ Wll,WR IWRTHRI J\r- INOlEIl 1 '-_______' \.______________-:--:-_ IRDHRI IID,RD (NDTE21 ____________________________ -1 '1.1- rL TLlC/9329-B MODEM Controls Timing Wl~ I\ ~ \ ~~~: I-.. D.-~:~I-------I- ..... '---.7",------- ~~ \ ! CTI.IIIII.mi 'I \1 . 'ITERRU'Y jr---..... \ r\ I (:::., -~I----'-~ A'---:-~_I-,,,___J·~rt.t: I~ (NDTE2) - I iii \ ,r--- TLlC/9329-9 Nota 1: See Write Cycle Timing Note 2: See Read Cycle Timing 4-9
5.0 Block Diagram INTERNAL DATA IUS D7· DD .. A, A, ,so RUK DDIS CSOUT XI. XOUT POWER{~+5V SUPPLY ~GND m 6TJi DiR DCD III jjjjfi iiiiT'l 13 """ TL/C/9329-IO Nota: Applicable pinout numbers are included within parenthesis. 6.0 Pin Descriptions The following describes the function of all UART, pins. Some of these descriptions reference internal circuits. In the following descriptions, a low represents a logic 0 (OV nominal) and a high represents a logic 1 (+2.4V nominal). 6.1 INPUT SIGNALS Chip Select (CSO, CS1, CS2), Pins 12-14: When CSO and CSt are high and CS2 is low, the chip is selected. This enables communication between the UART and the CPU. The positive edge of an active Address Strobe signal latches the decoded chip select signals, completing chip selection. If ADS is always low valid chip selects should stabilize according to the tcsw parameter. Read (RD, RD), Pins 22 and 21: When RD is high or RD is low while the chip is selected, the CPU can read status information or data from the selected UART register. Note: Only an active RD or RD input is required to transfer data from the UART during a read operation. Therefore, tie either the RD input permanent· Iy low or the Rl5 input permanently high, when tt is not used. Write (WR, WR), Pins 19 and 18: When WR is high or WR is low while the chip is selected, the CPU can write control words or data into the selected UART register. Nota: Only an active WR or Wi'! input is required to transfer data to the UART during a write operation. Therefore, tie either the WR input perma· nently low or the WI'! input permanently high, when tt is not used. Address Strobe (ADS), Pin 25: The positive edge of an active Address Strobe (ADS) signal latches the Register Select (AO, A1, A2) and Chip Select (CSO, CS1, CS2) signals. Note: An active AD!! input is required when the Register Select (AO. A I. A2) signals are not stable for the duration of a read or write operation. If not required. tie the AD!! Input permanently low. Register Select (AD, AI, A2), Pins 26-28: Address signals connected to these 3 inputs select a UART register for the CPU to read from or write to during data transfer. A table of registers and their addresses is shown below. Note that the state of the Divisor Latch Access Bit (DLAB), which is the most significant bit of the Line Control Register, affects the selection of certain UART registers. The DLAB must be set high by the system software to access the Baud Generator Divisor Latches. 4-10
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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~ ..,. r---------------------------
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ ,--------------------------------
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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Page 386 and 387: 00044 F90a :J- 226 Z • 227 MOVE A
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Page 390 and 391: Section 3 ISDN Components
Page 392 and 393: Introduction To National Semiconduc
Page 394 and 395: NSC Solutions for Layers 2 and 3 Na
Page 396 and 397: NSC Solutions: Systems Level Basic
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Page 400 and 401: ~National ~ Semiconductor PRELIMINA
Page 402 and 403: ISDN DEFINITIONS "B" Channel, or DS
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Page 407 and 408: Section 4 Contents INS8250/INS8250-
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Page 411 and 412: 3.0 AC Electrical Characteristics T
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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.----------------------------------
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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