~ National ~ Semiconductor - Al Kossow's Bitsavers

7.0 CPU Registers
INTRODUCTION
The CPU can address a total of 44 8-bit registers, providing
access to:
• 20 general purpose registers
• 8 configuration and control registers
• 4 transceiver access registers
• 2 8-bit accumulators
• 4 1 6-bit poi nters
• 16-bit timer
• 16-byte data stack
• address and data stack pointers
The registers are organized as shown in Figure 13. The first
12 locations, RO-R11, are arranged in two groups of
banked registers: Group A (RO-R3) and Group B (R4-R11).
Each group contains a Main and an Alternate bank, only
one of which is active and thus can be accessed in program
execution. Switching between the banks is performed by the
exchange instruction EXX, which uses a two-bit field to select
which registers occupy RO-R3 and R4-R11.
Registers in the RO-R11 address space are allocated in a
manner that minimizes the need to switch between banks:
Main A
CPU control and transceiver
status
Alternate A CPU and transceiver
configuration
Main B
Alternate B
8 general purpose
4 transceiver access,
4 general purpose
The BCP powers-up in Alternate bank A, Alternate bank B.
This allows the initialization registers to be accessed without
bank switching. When running a non-transceiver task, Main
bank A and Main bank B are typically switched in, allowing
access to the CPU control and transceiver status registers
and eight general purpose registers. When the transceiver
needs attention, Alternate bank B can be switched active
which allows access to the transceiver registers.
For those instructions that require two operands, R8, (each
bank) is designated as the accumulator and provides the
second operand. However, the result of such an operation
is stored back in the accumulator only if it is specified as the
destination.
Of the 38 instructions which have direct register access, 28
can address all 32 locations, the remaining 10 instructions
(those with an immediate data field) being limited to
RO-R15. These instructions, however, still have access to
all registers required for transceiver operation, together with
the CPU control and status registers, 12 general purpose
registers and two of the index registers.
In this chapter, two descriptions of the special function registers
are provided. The Register Overview section describes
the function of each bit field arranged by the registers
in which they occur; this section is useful for decoding
register contents and becoming familiar with the register
set. The Bit Definition Table lists the function and power-up
state of each bit field arranged by the function that it is
associated with; this section is useful in programming the
BCP. These sections are prefaced by a Bit Index which
cross references each bit field into both the Register Overview
and Bit Definition Table.
A:
Alternate
OCR
iR CCR
ATR NCr
----
ACR
'FeR ICR
RTR
f-- GPO
TSR
~ GPl
rn;m- GP2
I
Main
RO
Rl
R2
R3
8: f-- GP3
GP4'
f-- GP4 (accumulator)
GP5'
GP5
I GP6'
r;r GP6
~
GP7
W (low byte)
W (high byte)
I X (low byte)
Inde. R eglsters I X (high byte)
(p olnters)
Y (low byte)
Y (high byte)
Z (low byte)
Z (high byte)
GP8
GP9
GP10
GPll
GP12
GP13
GP14
GP15
I
R4
R5
R6
R7
R8
R9
Rl0
Rll
I R12
I R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
_TR_L____ ~ R28
TImer ~ TRH : R29
I R30
Stacks liSP
OS : R31
FIGURE 13. Register Map
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