~ National ~ Semiconductor - Al Kossow's Bitsavers

5.0 Instruction Set Overview (Continued)
Indexed Addressing Modes
The Immediate-Relative mode adds an unsigned 8-bit im-
mediate number to the index register IZ forming a data byte
address. The Register-Relative mode adds the unsigned
8-bit value in the current accumulator, A, to anyone of the
index registers forming a data byte address. Both of these
indirect memory addressing modes are available only on the
MOVE instruction. Table IV shows the notation used for
these two addressing modes.
Indexed operands involve one of four possible CPU register
pairs referred to as the index registers. Figure 1 illustrates
how the index registers map into the CPU Register Set.
Note that the index registers are 16 bits wide.
Index registers allow for indirect memory addressing and
usually contain data memory addresses, although, the
LJMP instruction can use index registers to hold instruction
memory addresses. Most of the instructions that allow
memory indirect addressing, (i.e. the use of index registers),
also allow pre-incrementing, post-incrementing, or post-decrementing
of the index register contents during instruction
execution, if desired. Table III lists the notations used for the
index register modes.
Immediate-Relative and Register-Relative
Address Modes
INSTRUCTION SET OVERVIEW
The BCP's RISC instruction set contains seven categories
of instructions: Data Movement, Integer Arithmetic, Logic,
Shift-Rotate, Comparison, Program Flow, and Miscellane-
Index CPU Register Pair Forming Index Register ous. Utilizing these instructions, any communications task
Register (MSB) (LSB) and almost any general computing task can be easily per-
I I I I I I I I I I I I I I I I I
IW R13 R12
formed.
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Data Movement Instructions
The MOVE instruction is responsible for all the data transfer
IX I I I I I I I I I I I I I I I I operations that the BCP can perform. Moving one byte at a
R15 R14 I time, five different types of transfer are allowed: register to
15 87 0 register, data memory to register, register to data memory,
instruction memory to register, and instruction memory to
IY
I I I I I I I I I I I I I I I I data memory. Table V lists all the variations of the MOVE
R17 R16 I instruction.
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IZ
I I I I I I I I I I I I I I I I R19 R18 I
15 87 0
FIGURE 1. Index Register Map
Notation
TABLE III. Index Register Addressing Mode Notations
Meaning
[lrl
Index Register, Contents Not Changed
[lr-I
Index Register, Contents Post-Decremented
[lr+1
Index Register, Contents Post-Incremented
[ +Irl Index Register, Contents Pre-Incremented
[mlrl
General Notation I ndicating that Any of the Above Modes Is Allowed
Note: [] denotes indirect memory addressing and is part of the instruction syntax.
TABLE IV. Relative Index Register Mode Notations
Notation
[lZ + nl
[lr + Al
Type of Action Performed to Calculate a Data Memory Address
IZ + Immediate Number (unsigned) ~ Data Memory Address
Index Register + Current Accumulator (unsigned) ~ Data Memory Address
Note: [] denotes indirect memory addressing and is part of the instruction syntax.
TABLE V. Data Movement Instructions
Syntax Instruction Operation Addressing Modes
MOVERs, Rd register ~ register Register, Register
MOVE Rs, [mlrl register ~ data memory Register, Indexed
MOVE [mlrl, Rd data memory ~ register Indexed, Register
MOVE Rs, [lr + Al register ~ data memory Register, Register-Relative
MOVE [lr + A), Rd data memory ~ register Register-Relative, Register
MOVE rs, [lZ + nl register ~ data memory Limited Register, Immediate-Relative
MOVE [lZ + nl, rd data memory ~ register Immediate-Relative, Limited Register
MOVE n, rd instruction memory ~ register Immediate, Limited Register
MOVE n, [lrl instruction memory ~ data memory Immediate, Indexed
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