~ National ~ Semiconductor - Al Kossow's Bitsavers

6.0 Instruction Set Reference (Continued)
ANDA And with Accumulator
Syntax
ANDA Rs, Rd
ANDA Rs, [mlr)
Affected Flags
N,Z
Description
-register, register
-register, indexed
Logically ANDs the source register Rs to the active accumulator
and places the result into the destination specified.
The destination may be either a register, Rd, or data memory
via an index register mode, [mlr]. Note that register bank
selection determines which accumulator is active.
Example
This example demonstrates a way to quickly unload all 11
bits of the Receiver FIFO when the FIFO is full. The example
assumes that the index register IZ points to the location
in data memory where the information should be stored.
EXX 1,1 ;select alternate banks
MOVE 00000111B, A ;place the {TSR} mask
; into the accumulator
Pop the first word from the receiver FIFO
ANDA TSR, [IZ+] ;read bits 8, 9, & 10
MOVE RTR, [IZ + ] ;pop bits 0-7
Pop the second word from the receiver FIFO
ANDA TSR, liZ + ]
MOVE RTR, liZ + ]
Pop the third word from the receiver FIFO
ANDA TSR, liZ + ]
MOVE RTR, liZ + ]
Instruction Format
ANDA Rs, Rd
I
Rd
15 9 4
ANDA
RS,[mlr]
1 11011101110101 1 1 1 1 1 1 1
_ Opcode .m.lr. Rs _
15 8 6 4 0
00 - post-decrement
01 - no change
10 - post Increment
11 - pre-increment
Rs
l
OO-IW
01 - IX
10 - IY
11 - IZ
o
TL/F/9336-7
BIT Bit Test
Syntax
BIT rs, n -limited register, immediate
Affected Flags
N,Z
Description
Performs a bit level test by logically ANDing the source register
rs to the immediate value n. The affected flags are
updated, but the result is not saved. Note that only the active
registers RO-R15 may be specified for rs. The value n
is 8 bits wide.
Example
Poll the Transmitter FIFO Empty flag [TFE] in the Network
Command Flag register {NCF}, R1, waiting for the Transmitter
to send the current FIFO data.
EXX 0,1 ;select main A, alt B
Poll: BIT 10000000B,NCF ;AII data sent yet?
JZ Poll ; No, poll TFE
; Yes, send next byte(s)
Instruction Format
15 11
T-states
2
Bus Timing
Figure 7
Operation
rs AND n
n
rs
3 0
T-states
ANDA Rs, Rd
ANDA Rs, [mlr)
Bus Timing
ANDA Rs, Rd
ANDA Rs, [mlr]
-2
-3
Operation
ANDA Rs, Rd
Rs AND accumulator -
ANDA Rs, [mlr)
Rs AND accumulator -
-Figure 7
-Figure 12
Rd
data memory
2-106