~ National ~ Semiconductor - Al Kossow's Bitsavers

8.0 Remote Interface and Arbitration System (Continued)
The last possible Memory Selection is Instruction Memory, state machine (RASM) loops in state RSA. If [LOR) is set
[MS1-0) = 01. The two possible next states for an IMEM high, RASM will loop in RSA indefinitely. If the BCP CPU
access depend on if RASM is expecting the low byte or high needs to access Data Memory at this time (and LOCK is
byte. Instruction words are accessed low byte then high high), it can still do so. A local access is requested by the
byte and RASM powers up expecting the low Instruction Timing Control Unit asserting the Local Bus Request
byte. The internal flag that keeps track of the next expected (LCL-BREQ) signal. A local bus grant will be given by RASM
Instruction byte is called the High Instruction Byte flag (HI B). if the buses are not being used (as is the case in RSA).
If HIB is low, the next state is RS05 and the low instruction XACK is taken low as soon as RAE*REM-RD is true, rebyte
is MUXed to the AD bus. If HIB is "1 ", the high instruc- gardless of an ongoing local access. RASM will move into
tion byte is MUXed to AD and RS06 is entered if HIB = 1. RSs on the next clock after RAE*REM-RD is asserted and
An IMEM access, like a DMEM access, is subject to wait there is no local bus request. No further local bus requests
states and these states will be looped on until all pro- will be granted until the BCP enters the Termination Phase.
grammed instruction memory wait states have been insert- If the BCP CPU initiates a Data Memory Access after RSA,
ed.
the Timing Control Unit will be waited and the BCP CPU will
All the RSo states eventually move to their corresponding remain in state T Wr until the Remote Access reaches the
RSE states on the clock after the wait state conditions, if Termination Phase.
any, are met. The RSE states are looped upon until On the next clock, RASM enters RSc and LCL is asserted
RAE*REM-RD is deasserted and WAIT is high. LCL is still along with XACK. The wait state counters, ilW and iow, are
high in this state and A remains in TRI-STATE. AD will also loaded in this state lrom [lW1-0) and [DW2-0), respectivestay
in TRI-STATE il the access was to DMEM. XACK is Iy, in (OCR). The A bus (and AD il the access is to Data
taken back high to indicate that data is now valid on the Memory) now goes into TRI-STATE and the Access Phase
read. II XACK is connected to a Remote Processor wait pin, begins.
it is no longer waited and can now terminate its read cycle. The state machine can move into one 01 several states de-
This state begins the Termination Phase. The action speci- pending CMD and [MS1-0) on the next clock. XACK and
lied in the conditional box is only executed while RAE*REM- LCL are still asserted in all the possible next states. II CMD
RD is asserted-a clock edge is not necessary.
is high, the access is to (RIC) and the next state will be
On the CPU-CLK after RAE*REM-RD is deasserted, RASM RS01. Since the delault state 01 AD is (RIC), it will not
enters RSF, where LCL is high and the TRI-STATE condi- transition in this state. The live other next states all have
tion in RSE remains in effect. The next clock brings the state CMD low and depend on the Memory Select bits.
machine back to RSA state where it will loop until another II [MS1-0) is 10 or 11 the state machine will enter either
Remote Access is initiated. If the access was to IMEM, then RS02 or RS03 and the low or high bytes of the Program
the last action 01 the remote access belore returning to RSA Counter, respectively, will be read.
is to switch HIB and increment the PC il the high byte was [MS1-0) = 00 designates a Data Memory access and
read.
moves RASM into RS04' READ will be asserted in this state
The example in Figure 26 shows the BCP executing the first and A and AD continue to be at TRI-STATE. This allows the
01 two consecutive Data Memory reads when REM-RD goes Remote Processor to drive the Data Memory address for
low. In response, XACK goes low waiting the remote proc- the read. Since DMEM is subject to wait states, RS04 is
essor. At the end of the first instruction, although the BCP looped upon until all the wait states have been inserted.
begins its second read by taking ALE high, the RASM now The last possible Memory Selection is Instruction Memory,
takes control of the bus and takes LCL high at the end of [MS1-0) = 01. The two possible next states lor the IMEM
T1· A one T-state delay is built into this transfer to ensure access depend on if RASM is expecting the low byte or high
that READ has been deasserted belore the data bus is byte. Instruction words are accessed low byte then high
switched. The Timing Control Unit is now waited, inserting byte and RASM powers up expecting the low Instruction
remote access wait states, T Wr, as RASM takes over.
byte. The internal Ilag that keeps track of the next expected
The remote address is permitted one T-state to settle on the Instruction byte is called the High Instruction Byte flag (HIB).
BCP address bus before READ goes low, XACK then re- If HIB is low, the next state is RS05 and the low instruction
turns high one T-state plus the programmed Data Memory byte is MUXed to the AD bus. If HIB is "1" , the high instrucwait
state, TWd later, having satislied the memory access tion byte is MUXed to AD and RS06 is entered if HIB = 1.
time. The Remote Processor will respond by removing An IMEM access, like a DMEM access, is subject to wait
REM-RD to which the BCP in turn responds by removing states and these states will be looped on until all pro-
READ. Following the removal 01 READ, the BCP waits till grammed instruction memory wait states have been insertthe
end 01 the next T-state before taking LCL low, again ed.
ensuring that the read cycle has concluded before the bus
is switched. Control is then returned to the Timing Control
Unit and the local memory read continues.
Latched Read
This mode differs from the Buffered Read mode in the way
the access is terminated. A latched Read cycle ends after
the data being read is valid and the termination doesn't wait
for the trailing edge of REM-RD. Therefore the Arbitration
and Access Phases of the Latched Read mode are the
same as for the Buffered Read mode. The complete flow
chart for the Latched Read mode is shown in Figure 27.
Until a Remote Read is initiated (RAE*REM-RD true), the
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All the RSo states move to their corresponding RSE states
on the CPU-CLK after wait state conditions are met and
WAIT is high. LCL is asserted in all RSE states and A remains
in TRI-STATE (and AD if the access is to Data Memory).
XACK returns high in this state, indicating that data is
valid so that it can be externally latched. The action specific
to each RSo state remains in effect during the first half of
the RSE cycle (Le. READ is asserted in the first half of
RSE4). This hall T-state of hold time is provided to guarantee
data is latched when XACK goes high. This state begins
the Termination Phase.