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5.0 Instruction Set Overview (Continued)
Shift and Rotate Instructions
The shift and rotate instructions operate on any of the 8-bit
CPU registers. The BCP supports shift left, shift right, and
rotate operations. Table VIII lists the shift and rotate instructions.
Comparison Instructions
The BCP utilizes two comparison instructions. The CMP instruction
performs a two's complement subtraction between
a register and immediate data. The BIT instruction tests selected
bits in a register by ANDing it with immediate data.
Neither instruction stores its results, only the ALU flags are
affected. Table IX lists both of the comparison instructions.
Program Flow Instructions
The BCP has a wide array of program flow instructions: unconditional
jumps, calls and returns; conditional jumps,
calls, and returns; relative or absolute instruction addressing
on jumps and calls; a specialized register field decoding
jump; and software interrupt capabilities. These instructions
redirect program flow by changing the Program Counter.
The unconditional jump instructions support both relative instruction
addressing, the (JuMP instruction), and absolute
instruction addressing, (the Long JuMP instruction), using
the following addressing modes: Immediate, Register, Absolute,
and Indexed. Table X lists the unconditional jump instructions
and their variations.
The conditional jump instructions support both relative instruction
addressing and absolute instruction addressing using
the Immediate and Absolute addressing modes. The
conditional relative jump instruction tests flags in the Condition
Code Register, {CCR J. and the Transceiver Status
Register, (TSR). Two possible syntaxes are supported for
the conditional relative jump instruction; see Table XI.
Table XII lists the various flags "f" that the conditional JMP
instruction can test and Table XII I lists the various conditions
"cc" that the Jcc instruction can test for. Keep in
TABLE VIII. Shift and Rotate Instructions
Syntax I nstruction Operation Addressing Mode
SHL Rsd,b Register
SHR
Rsd,b
~ i i i i i i i III
~o
Rod
i i i i i i i
o~ •
Rod
~
Register
4
i i i i i i i
ROT Rsd,b III
~
Register
Note: "b" = the number of bit shifts/rotates to perform.
Rod
Syntax
TABLE IX. Comparison Instructions
Instruction Operation Addressing Mode
CMP rs, n register - n Limited Register
BIT rs, n register & n Limited Register
Note: & = logical AND operation
TABLE X. Unconditional Jump Instructions
Syntax Instruction Operation Operand Range Addressing Mode
JMP n PC + n (sign extended) ~ PC -128, +127 Immediate
JMP Rs PC + Rs (sign extended) ~ PC -128, +127 Register
LJMP nn nn~PC O,64k Absolute
LJMP [lrl Ir~PC O,64k Indexed
Note: PC = Program Counter; contents initially points to instruction following jump.
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