~ National ~ Semiconductor - Al Kossow's Bitsavers

8.0 Remote Interface and Arbitration System (Continued)
On the next clock the state machine will enter RSF and LCL
will be deasserted. Once the state machine enters RSF, the
Remote Processor is no longer using the buses and the
BCP CPU will be granted the buses if LCL-BREQ is asserted.
If a local bus request is made, a local bus grant will be
given to the Timing Control Unit. If the preceding access
was a read of IMEM, then HIB is switched and if the access
was to the high byte of IMEM then the PC is incremented. If
RAE·REM-RD is deasserted at this point, the next clock will
bring RASM back to RSA where it will loop until another
Remote Access is initiated. RSG is entered if RAE*REM-RD
is still true. RASM will loop in RSG until RAE*REM-RD is no
longer active at which time the state machine will return to
RSA·
In Figure 15, the BCP is executing the first of two Data
Memory reads when REM-RD goes low. In response, XACK
goes low, waiting the Remote Processor. At the end of the
first instruction, although the BCP begins its second write by
taking ALE high, the RASM now takes control of the bus
and deasserts LCL at the end of T 1. A one T -state delay is
built into this transfer to ensure that READ has been deasserted
before the data bus is switched. The Timing Control
Unit is now waited, inserting remote access wait states,
T WR, as RASM takes over.
The remote address is permitted one T -state to settle on the
BCP address bus before READ goes low, XACK then returns
high one T-state plus the programmed Data Memory
wait state, TWd later, having satisfied the memory access
time. READ returns high a half T -state later, ensuring sufficient
hold time, followed by LCL being reasserted after an
additional half T -state, transferring bus control back to the
BCP. The Remote Processor responds to XACK by removing
REM-RD, although by this time the BCP is well into its
own memory read.
Slow Buffered Write
The timing for this mode is the same as the Buffered Read
mode. The complete flow chart for the Slow Buffered Write
mode is shown in Figure 29. Until a Remote Write is initiated
(RAE*REM-WR true), the state machine (RASM) loops in
state RSA. If [LOR) is set high, RASM will loop in RSA indefinitely.
If the BCP CPU needs to access Data Memory at this
time (and LOCK is high), it can still do so. A local access is
requested by the Timing Control Unit asserting the Local
Bus Request (LCL-BREQ) signal. A local bus grant will be
given by RASM if the buses are not being used (as is the
case in RSA).
XACK is taken low as soon as RAE·REM-WR is true, regardless
of an ongoing local access. RASM will move into
RSs on the next clock after RAE·REM-WR is asserted and
there is no local bus request and [LOR) = O. No further
local bus requests will be granted until the remote access is
complete and RASM returns to RSA. If the BCP CPU initiates
a Data Memory access after RSA, the Timing Control
Unit will be waited and the BCP CPU will remain in state TWr
until completion of the remote access.
On the next CPU-CLK, RASM enters RSe and LCL is asserted
along with XACK. The wait state counters, ilw and
iDW, are loaded in this state from (iW1-0) and [DW2-0],
respectively, in [DCR}. The A and AD buses now go into
TRI-STATE and the Access Phase begins. The state machine
can move into one of several states, depending on
the state of CMD and [MS1-0), on the next clock. XACK
and LCL are still asserted in all the possible next states. If
CMD is high, the access is to [RIC} and the next state will
be RSD1. The path from AD to [RIC} opens in this state.
The five other next states all have CMD low and depend on
the Memory Select bits. If [MS1-0] is 10 or 11 the state
machine will enter either RSD2 or RSD3 and the low or high
bytes of the Program Counter, respectively, will be written.
[MS1-0] equal to 00 designates a Data Memory access
and moves RASM into RSD4. WRITE will be asserted in this
state and A and AD continue to be atTRI-STATE. This allows
the Remote Processor to drive the Data Memory address
and data buses for the write. Since OM EM is subject
to wait states, RSD4 is looped upon until all the programmed
data memory wait states have been inserted.
The last possible Memory Selection is Instruction Memory,
[MS1-0] = 01. The two possible next states for IMEM depend
on whether RASM is expecting the low byte or high
byte. Instruction words are accessed low byte, then high
byte and RASM powers up expecting the low Instruction
byte. The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HI B).
If HIB is low, the next state is RSD5 and the low instruction
byte is written into the holding register, ILAT. If HIB is "1",
the high instruction byte is moved to 115-8 and the value in
ILAT is moved to 17-0. At the same time, IWR rises, beginning
the write to instruction memory. An IMEM access, like a
DMEM access, is subject to wait states and these states will
be looped on until all programmed Instruction Memory wait
states have been inserted.
All the RSD states eventually move to their corresponding
RSE states on the clock after the wait state conditions, if
any, are met. The RSE states are looped until RAE·REM­
WR is deasserted and WAIT is high. LCL is still asserted in
this state, but XACK is taken back high to indicate that the
remote access can be terminated. If XACK is connected to
a Remote Processor wait pin, it can now terminate its write
cycle. This state begins the Termination Phase. The action
specified in the conditional box is only executed while
RAE*REM-WR is asserted-a clock edge is not necessary.
On the CPU-CLK after RAE·REM-WR is deasserted, RASM
enters RSF. where LCL is asserted and the BCP A and AD
buses are still in TRI-STATE. The next clock brings the state
machine back to RSA state where it will loop until another
Remote Access is initiated. If the access was to IMEM. then
the last action of the remote access before returning to RSA
is to switch HIB and increment the PC if the high byte was
read.
In Figure 30, the BCP is executing the first of two consecutive
Slow Buffered Writes to Data Memory when REM-WR
goes low. In response, XACK goes low. waiting the Remote
Processor. At the end of the first instruction, although the
BCP begins its second write by taking ALE high, RASM now
takes control of the bus and deasserts LCL at the end of T 1.
A one T -state delay is built into this transfer to ensure that
WRITE has been deasserted before the data bus is
switched. The Timing Control Unit is now waited, inserting
remote access wait states. T W" as RASM takes over.
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