~ National ~ Semiconductor - Al Kossow's Bitsavers

10.0 Transceiver (Continued)
{also in the (NCFl register) indicates different information
depending on the selected protocol. In 3270 and 3299;
[DEME) is set when B10 of the received frame does not
match the locally generated odd parity on bits B2-B9 of the
received frame. This flag is not part of the receiver error
logic, it functions only as a status flag to the CPU. These
flags are decoded from the last location in the FIFO and are
valid only when [DA VI is asserted; they are cleared by reading
{RTR I and should be checked before accessing that
register.
5250 Modes
The biphase data is inverted in the 5250 protocol relative to
3270/3299 (see the Protocol section-IBM 5250). Depending
on the external line interface circuitry, the transceiver's
biphase inputs and outputs may need to be inverted by asserting
the [RIN) (Receiver INvert) and [TIN) (Transmitter
INvert) control bits in {TMR!.
For information on how data must be organized in {TCR I
and {RTR I for input to the transmitter, and how data extracted
from a received frame is organized by the receiver
and mapped into {TSR I and {RTR l. See Figure 43.
To transmit a 5250 message, the least significant 4 bits of
{TCR I must first be set up with the correct address and
parity control information. The station address field (B4-B6)
is defined by {TCR[0-2)l. and [OWPI controls the type of
parity (even or odd) calculated on B4-B15 and transmitted
as B3. When the a-bit data byte is written to {RTR I, the
resulting composite 12-bit word is loaded into the transmit
FIFO, starting the transmitter. The same {TCRI contents
can be used for more than one frame of a multi-frame transmission,
or changed for each frame.
The 5250 protocol defines bits BO-B2 as fill bits which the
transmitter automatically appends to the parity bit (B3) to
form the 16-bit frame. Additional fill bits may be inserted
between frames of a multi-frame transmission by loading
the fill bit register, {FBR I, with the one's compliment of the
number of fill bits to be transmitted. A value of FF (hex),
corresponding to the addition of no extra fill bits. At the
conclusion of a message the transmitter will return to the
idle state after transmitting the 3 fill bits of the last frame (no
additional fill bits will be transmitted).
As shown in Table XXVI, the transceiver can operate in 2
different 5250 modes, designated "promiscuous" and "nonpromiscuous".
The transmitter operates in the same manner
in both modes.
In the promiscuous mode, the receiver passes all received
data to the CPU via the FIFO, regardless of the station address.
The CPU may determine which station is being addressed
by reading ITSR [0-211 before reading {RTR!.
In the non-promiscuous mode, the station address field
(B4-B6) of the first frame must match the 3 least significant
bits of the Auxiliary Transceiver Register, (ATR[0-2) I, before
the receiver will pass the data on to the CPU. II no
match is detected in the first frame of a mes!!age, and if no
errors were found on that frame, the receiver will reset to
idle, looking for a valid start sequence. If an address match
is detected in the first frame of a message, the received
data is passed on to the CPU. For the remainder of the
message all received frames are decoded in the same manner
as the promiscuous mode.
To maintain maximum flexibility, the receiver logic does not
interpret the station address or command fields in determining
the end of a 5250 message. The message typically ends
with no further line transitions after the third fill bit of the last
frame. This end of message must be distinguished from a
loss of synchronization between frames of a multi-byte
transmission condition by looking for line activity some time
after the loss of synchronization occurs. When the loss of
synchronization occurs during fill bit reception, the receiver
monitors the Line Active flag, [LAI, for up to 11 biphase bit
times (11 p.s at the 1 MHz data rate). If [LA) goes inactive at
any point during this period, the receiver returns to the idle
state, de-asserting [RA) and asserting [L TAl. II, however,
[LA) is still asserted at the end of this window, the receiver
interprets this as a real loss of synchronization and flags the
appropriate error condition to the CPU. (See the Receiver
Errors section in this Chapter.)
7 654 3 2 I 0
RTR I B71 881 B9IBIOUl1lB12IBI3IBI41
7 6 5 4 3 2 0
lowpi 84 1 85 1 86 ITeR
Twlnax tranltnlalon
T
tranltnit
*
Sync DO DI D2 D3 D4 D5 D6 D7 AD AI A2 Par
T
reoelve
*
7 6 543 2 I 0 7 6 543 2 I 0
RTR I 871 881 B9IBIOUl1lB12IB13IBI41
IB41BSIB61TCR
FIGURE 43. 5250 Frame Assembly/Disassembly Description
TUF 19336-49
2-177