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8.0 Remote Interface and Arbitration System (Continued) Latched Write This mode executes a write without waiting the Remote Processor-XACK isn't normally taken low. The complete flow chart for the Latched Write mode is shown in Figure 33. Until a Remote Write is initiated (RAE*REM-WR true), the state machine (RASM) loops in state RSA. If the BCP CPU needs to access Data Memory at this time (and LOCK is high), it can still do so. A local access is requested by the Timing Control Unit asserting the Local Bus Request (LCL-BREQ) signal. A local bus grant will be given by RASM if the buses are not being used (as is the case in RSA). RASM will move into RSs on the next clock after RAE*REM-WR is asserted. XACK is not taken low and therefore the RP is not waited. The state machine will loop in RSs until the RP terminates its write cycle-until RAE*REM-WR is no longer true. The external address and data latches are typically latched on the trailing edge of REM-WR. A local bus request will still be serviced in this state. Next, RASM enters RSc and WR-PEND is asserted to prevent overwrite of the external latches. Since the RP has completed its write cycle, another write or read can happen at any time. Any Remote Read cycle (RAE*REM-RD) or Remote Write cycle (RAE*REM-WR) occurring after the state machine enters RSc will take XACK low. A local access initiated before or during this state must be completed before RASM can move to RSo. Once RSo is entered, though, no further local bus requests will be granted until the BCP enters the Termination Phase. If the BCP CPU initiates a Data Memory Access after RSc, the Timing Control Unit will be waited and the BCP CPU will remain in state T Wr, until the RASM enters RSH. On the first clock where there is no local bus request the state machine enters RSE. WR-PEND and LCL continue to be asserted in this state and the data and instruction wait state counters, iow and ilW, are loaded from [DW2-0] and [IW1-0], respectively, in {DCR}. Any remote accesses now occurring will take XACK low and wait the Remote Processor. The state machine will move into one of several states on the next clock, depending on the state of CMD and [MS1-0]. WR-PEND and LCL are still asserted in all the possible next states. If CMD is high, the access is to {RIC} and the next state will be RSF1. The path from AD to {RIC} opens in this state. The five other next states all have CMD low and depend on the Memory Select bits. If [MS1-0] is 10 or 11 the state machine will enter either RSF2 or RSF3 and the low or high bytes of the Program Counter, respectively, will be loaded. [MS1-0] = 00 designates a Data Memory access and moves RASM into RSF4. WRITE will be asserted in this state and A and AD continue to be at TRI-STATE. This allows the Remote Processor to drive the Data Memory address and data for the write. Since DMEM is subject to wait states, RSF4 is looped upon until all the wait states have been inserted. The last possible Memory Selection is Instruction Memory, [MS1-0] = 01. The two possible next states for IMEM depend on if RASM is expecting the low byte or high byte. Instruction words are accessed low byte then high byte and RASM powers up expecting the low Instruction byte. The internal flag that keeps track of the next expected Instruction byte is called the High Instruction Byte flag (HIB). If HIB is low, the next state is RSF5 and the low instruction byte is written Into the holding register, ILAT. If HIB is "I", the high instruction byte is moved to 115-8 and the value in ILAT is moved to 17 -0. At the same time IWR rises and the write to Instruction Memory is begun. An IMEM access, like a DMEM access, is subject to wait states and these states will be looped on until all programmed instruction memory wait states have been inserted. <strong>Al</strong>l the RSF states converge to a single decision box that tests WAIT. If WAIT is low then the state machine loops back to RSF, otherwise RASM will move on to RSG. LCL and WR-PEND are still asserted in this state but the actions specific to the RSF states have ended (i.e. WRITE will no longer be asserted). The next CPU-CLK moves RASM into RSH, the last state in the state machine. LCL is no longer asserted, but WR-PEND is still low. XACK will be taken low if a Remote Access is initiated. If the just completed access was to IMEM, HIB will be switched. <strong>Al</strong>so, the PC will be incremented if the high byte was written. A local access will be granted if LCL-BREQ is asserted in this state. If another Remote Write is pending, the state machine takes the path to RSs where that write will be processed. A pending Remote Read will return to the RSA in either the Buffered or Latched Read sections (not shown in Figure 33) of the state machine. And if no Remote Access is pending, the machine will loop in RSA until the next access is initiated. In Figure 35, the BCP is executing the first of two Data Memory writes when REM-WR goes low. The BCP takes no action until REM-WR goes back high, latching the data and making a remote access request. The BCP responds to this by taking WR-PEND low. At the end of the first instruction although the BCP begins its second write by taking ALE high, RASM now takes control of the bus and deasserts LCL at the end of T 1. A one T -state delay is built into this transfer to ensure that WRITE has been deasserted before the data bus is switched. Timing Control Unit is now waited, inserting remote access wait states, T Wr, as RASM takes over. The remote address is permitted one T -state to settle on the BCP address bus before WRITE goes low. WRITE then returns high one T-state plus the programmed Data Memory wait state, T Wd later, having satisfied the memory access time, and one T -state later LCL is reasserted, transferring bus control back to the BCP. In this example, REM-WR goes low again during the remote write cycle which, since WR-PEND is still low, causes XACK to go low to wait the Remote Processor. XACK and WR-PEND go back high at the same time as LCL goes low, allowing the second data byte to be latched on the next trailing edge of REM-WR. The BCP is now shown executing a local memory write, with remote data still pending in the latch. At the end of this instruction, the BCP begins executing a series of internal operations which do not require the bus. RASM therefore takes over and, without waiting the Timing Control Unit, executes the Remote Write. 2-163
DP8344A ~ ~ co o ::0 CD 3 o -CD ::s -CD ::::. I» n CD I» ::s c. ., » C" ., ;:::; I» -O· ::s en ~ -CD 3 '§ a ::J c: ~ Irw=n[IWI_O] WR-PEND ~ TRI-STATE A, AD I RS[ i FIGURE 33. Flow Chart of Latched Write Mode TLIF /9336-A 1
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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4.0 Electrical Specifications (Cont
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Page 348 and 349: Decoding Bit Fields with the JRMK I
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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4.0 Timing Waveforms (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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5.0 Block Diagram AO A, A2 CSD CSI
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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TABLE III. Remote Digital Loopback
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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