~ National ~ Semiconductor - Al Kossow's Bitsavers

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15.0 Switching Characteristics. (Continued)
TXC
COL
Serial Timing-Transmit (Collision)
---Q'----~ i-------H"'---l--
.~ tcdj------+l
TXE
TL/F/9345-53
Symbol Parameter Min Max Units
tcolw
tcdj
Collision Detect Width
Delay from Collision to First
Bit of Jam (Note 1)
tjam Jam Period (Note 2)
2
8
32
txcyc
cycles
txcyc
cycles
txcyc
cycles
Note 1: The NIC must synchronize to collision detect. If the NIC is in the middle of serializing a byte of data the remainder of the byte will be serialized. Thus the jam
pattern will start anywhere from 1 to 8 TXC cycles after COL is asserted.
Note 2: The NIC always issues 32 bits of jam. The jam is all 1 's data.
Reset Timing
BSCK
TXC
_________ ~~ ________________________......J
RESET
TL/F/9345-54
Symbol Parameter Min Max
rstw Reset Pulse Width (Note 1)
8
Units
BSCK Cycles or TXC Cycles
(Note 2)
Nole 1: The RESET pulse requires that BSCK and TXC be stable. On power up, RESET should not be raised until BSCK and TXC have become stable. Several
registers are affected by RESET. Consult the register descriptions for details.
Note 2: The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low.
If BSCK < TXC then RESET ~ B X BSCK
If TXC < BSCK then RESET ~ B X TXC
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