~ National ~ Semiconductor - Al Kossow's Bitsavers

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10.0 Internal Registers (Continued)
10.3 Register Descriptions (Continued)
INTERRUPT STATUS REGISTER (ISR)
07H (READ/WRITE)
This register is accessed by the host processor to determine the cause of an interrupt. Any interrupt can be masked in the
Interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a "1" into the corresponding bit of the ISR. The INT
signal is active as long as any unmasked signal is set, and will not go low until all unmasked bits in this register have been
cleared. The ISR must be cleared after power up by writing it with all 1 'so
7 6 5 4 3 2 1 0
I RST I ROC I CNT I OVW I TXE I RXE I PTX I PRX I
Bit Symbol Description
00 PRX PACKET RECEIVED: Indicates packet received with no errors.
01 PTX PACKET TRANSMITTED: Indicates packet transmitted with no errors.
02 RXE RECEIVE ERROR: Indicates that a packet was received with one or more of the
following errors:
-CRC Error
-Frame Alignment Error
-FIFO Overrun
-Missed Packet
03 TXE TRANSMIT ERROR: Set when packet transmitted with one or more of the
following errors:
-Excessive Collisions
-FIFO Underrun
04 OVW OVERWRITE WARNING: Set when receive buffer ring storage resources have
been exhausted. (Local OMA has reached Boundary POinter).
05 CNT COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally
Counters has been set.
06 ROC REMOTE DMA COMPLETE: Set when Remote OMA operation has been
completed.
07 RST RESET STATUS: Set when N IC enters reset state and cleared when a Start
Command is issued to the CR. This bit is also set when a Receive Buffer Ring
overflow occurs and is cleared when one or more packets have been removed
from the ring. Writing to this bit has no effect.
NOTE: This bit does not generate an interrupt, it is merely a status indicator.
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