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9.0 Remote DMA The Remote DMA channel is used to both assemble packets for transmission, and to remove received packets from the Receive Buffer Ring. It may also be used as a general purpose slave DMA channel for moving blocks of data or commands between host memory and local butter memory. There are three modes of operation, Remote Write, Remote Read, or Send Packet. Two register pairs are used to control the Remote DMA, a Remote Start Address (RSARO, RSAR1) and a Remote Byte Count (RBCRO, RBCR1) register pair. The Start Address register pair point to the beginning of the block to be moved while the By1e Count register pair are used to indicate the number of by1es to be transferred. Full handshake logic is provided to move data between local buffer memory and a bidirectional liD port. REMOTE WRITE A Remote Write transfer is used to move a block of data from the host into local buffer memory. The Remote DMA will read data from the liD port and sequentially write it to local buffer memory beginning at the Remote Start Address. The DMA address will be incremented and the Byte Counter will be decremented after each transfer. The DMA is terminated when the Remote By1e Count register reaches a count of zero. REMOTE READ A Remote Read transfer is used to move a block of data from local buffer memory to the host. The Remote DMA will sequentially read data from the local butter memory, beginning at the Remote Start Address, and write data to the 1/0 port. The DMA address will be incremented and the By1e Counter will be decremented after each transfer. The DMA is terminated when the Remote Byte Count register reaches zero. SEND PACKET COMMAND Remote DMA Autoinitialization from Buffer Ring The Remote DMA channel can be automatically initialized to transfer a single packet from the Receive Buffer Ring. The CPU begins this transfer by issuing a "Send Packet" Command. The DMA will be initialized to the value of the Boundary Pointer register and the Remote By1e Count register pair (RBCRO, RBCR1) will be initialized to the value of the Receive Byte Count fields found in the Buffer Header of each packet. After the data is transferred, the Boundary Pointer is advanced to allow the buffers to be used for new receive packets. The Remote Read will terminate when the Byte Count equals zero. The Remote DMA is then prepared to read the next packet from the Receive Buffer Ring. If the DMA pointer crosses the Page Stop register, it is reset to the Page Start Address. This allows the Remote DMA to remove packets that have wrapped around to the top of the Receive Buffer Ring. Note 1: In order for the NIC to correctly execute the Send Packet Command, the upper Remote Byte Count Register (RBCR1) must first be loaded with OFH. Note 2: The Send Packet command cannot be used with 68000 type processors. 10.0 Internal Registers <strong>Al</strong>l registers are 8-bit wide and mapped into two pages which are selected in the Command register (PSO, PS1). Pins RAO-RA3 are used to address registers within each page. Page ° registers are those registers which are commonly accessed during NIC operation while page 1 registers are used primarily for initialization. The registers are partitioned to avoid having to perform two writelread cycles to access commonly used registers. o "'tJ 01) Co) co o o I ..... -Z en Co) I\) .... co o I ..... • I "0" TLiF/9345-17 1-65
.- r------------------------------------------------------------------------------------------, o 10.0 Internal Registers (Continued) 0) ~ 10.1 REGISTER ADDRESS MAPPING C') (/) Z ....... .- o 0) C') CO a.. C TLlF/9345-18 10.2 REGISTER ADDRESS ASSIGNMENTS Page 0 Address Assignments (PS1 = 0, PSO = 0) RAO-RA3 RD WR OOH Command (CR) Command (CR) 01H Current Local DMA Page Start Register Address 0 (CLDAO) (PSTART) 02H Current Local DMA Page Stop Register Address 1 (CLDA 1) (PSTOP) 03H Boundary Pointer Boundary Pointer (BNRY) (BNRY) 04H Transmit Status Transmit Page Start Register (TSR) Address (TPSR) 05H Number of Collisions Transmit Byte Count Register (NCR) Register 0 (TBCRO) 06H FIFO (FIFO) Transmit Byte Count Register 1 (TBCR 1) 07H Interrupt Status Interrupt Status Register (ISR) Register (ISR) 08H 09H Current Remote DMA Remote Start Address Address 0 (CRDAO) Register 0 (RSARO) Current Remote DMA Remote Start Address Address 1 (CRDA 1) Register 1 (RSAR1) OAH Reserved Remote Byte Count Register 0 (RBCRO) OBH Reserved Remote Byte Count Register 1 (RBCR 1) OCH Receive Status Receive Configuration Register (RSR) Register (RCR) ODH Tally Counter 0 Transmit Configuration (Frame <strong>Al</strong>ignment Register (TCR) Errors) (CNTRO) OEH Tally Counter 1 Data Configuration (CRC Errors) Register (DCR) (CNTR1) OFH Tally Counter 2 Interrupt Mask (Missed Packet Register (IMR) Errors) (CNTR2) Page 1 Address Assignments (PSl = 0, PSO = 1) RAO-RA3 RD WR OOH Command (CR) Command (CR) 01H Physical Address Physical Address Register 0 (PARO) Register 0 (PARO) 02H Physical Address Physical Address Register 1 (PAR1) Register 1 (PAR1) 03H Physical Address Physical Address Register 2 (PAR2) Register 2 (PAR2) 04H Physical Address Physical Address Register 3 (PAR3) Register 3 (PAR3) 05H Physical Address Physical Address Register 4 (PAR4) Register 4 (PAR4) 06H Physical Address Physical Address Register 5 (PAR5) Register 5 (PAR5) 07H Current Page Current Page Register (CURR) Register (CURR) 08H Multicast Address Multicast Address Register 0 (MARO) Register 0 (MARO) 09H Multicast Address Multicast Address Register 1 (MARl) Register 1 (MAR 1) OAH Multicast Address Multicast Address Register 2 (MAR2) Register 2 (MAR2) OBH Multicast Address Multicast Address Register 3 (MAR3) Register 3 (MAR3) OCH Multicast Address Multicast Address Register 4 (MAR4) Register 4 (MAR4) ODH Multicast Address Multicast Address Register 5 (MAR5) Register 5 (MAR5) OEH Multicast Address Multicast Address Register 6 (MAR6) Register 6 (MAR6) OFH Multicast Address Multicast Address Register 7 (MAR7) Register 7 (MAR7) 1-66
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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Page 118 and 119: PCC Connection Diagram 39.0. 39.0.
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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9.0 Timing and Load Diagrams (Conti
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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