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10.0 Internal Registers (Continued)
10.3 Register Descriptions (Continued)
INTERRUPT MASK REGISTER (IMR)
OFH(WRITE)
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status
Register (ISR). If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit
in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeroes.
7 6 5 4 3 2 1 0
I
- IRDCElcNTEloVVVEITXEEIRXEElpTXElpRXEI
Bit Symbol Description
DO PRXE PACKET RECEIVED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received.
01 PTXE PACKET TRANSMITTED INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet is transmitted.
02 RXEE RECEIVE ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet received with error.
03 TXEE TRANSMIT ERROR INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when packet transmission results in error.
04 OVVVE OVERWRITE WARNING INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to
store incoming packet.
05 CNTE COUNTER OVERFLOW INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when MSB of one or more of the Network Statistics
counters has been set.
06 RDCE DMA COMPLETE INTERRUPT ENABLE
0: Interrupt Disabled
1: Enables Interrupt when Remote DMA transfer has been completed.
07 reserved reserved
1-19