~ National ~ Semiconductor - Al Kossow's Bitsavers

8.0 Remote Interface and Arbitration System (Continued)
Arbitration Access Termination
REM-RD~~ __________________--J;---
CMD 'lllllI
WZZZ
XACK ' ....._____________ 1
ili 1 '....._-
AD
RIC
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(a) Remote Read Timing (RAE = 0)
Arbitration Access Termination
REM-WR~~ __________________ ~;---
CMD 'lllllI
XACK
ili
AD
,'--____
.J1
I
WZZZ
'....._-
RIC ) ( New RIC
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(b) Remote Write Timing (RAE = 0)
7 6 5 4
BIS SS FBW LR
3 2 1 0
LW lliIi±li±J
Memory Select Bits
00 - Data Memory
01 - Instruction Memory
10 - PC low byte
11 - PC high byte
Reads or writes of Data Memory (DMEM) are preceded by
setting the Memory Select bits in {RICl for a DMEM access:
[MS1,O] = 00. After that, the RP simply reads or
writes to BCP Data Memory as many times as it needs to. A
DMEM access, as well as a {RICl access, can be made
while the BCP CPU is executing instructions. All other accesses
must be executed with the BCP CPU stopped.
The timing for a Data Memory read and write are shown in
Figure 18. The access is initiated by asserting RAE and
REM-RD or REM-WR while CMD is low. The BCP responds
by bringing its address and data lines into TRI-STATE and
allowing the RP to control DMEM. READ is asserted in the
Access Phase of a Remote Read (a). It will stay low for a
minimum of one T -state, but can be extended by adding
programmable data wait states or by taking WAIT low.
WRITE is asserted in the Access Phase with a remote write.
It too is a minimum of one T-state and can be increased by
adding programmable wait states or by taking WAIT low.
Figure 19(c) shows the data path from the Program Counter
to the AD bus. Both high and low PC bytes can be written or
read through AD. The RP has independent control of the
high and low bytes of the Program Counter-the byte being
accessed is specified in the Memory Select bits. The high
byte of the PC is accessed by setting [MS1-0] = 11. Setting
[MS1-0] = 10 allows access to the low byte of the PC.
After the Memory Select bits are set by a Remote Write to
{RICl, the byte selected can be read or written by the RP
by executing a Remote Access with CMD low. This type
access as well as the instruction memory access must be
executed with the BCP CPU idle. Four accesses by the RP
are necessary to read or write both the high and low bytes
of the PC. Timing for a PC access is shown in Figure 19(aj
and (b). The PC becomes valid on a Remote Read (aj one
T -state after LCL rises and one T -state before XACK rises.
AD is in TRI-STATE while LCL is high for a Remote Write
(bj. Time in the Access Phase is two T-states if WAIT is not
asserted.
(c) RIC to AD Connectivity
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FIGURE 17. Generic RIC Access
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