~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics (Continued)
Serial Timing-Receive (Beginning of Frame)
TL/F/9345-49
Symbol Parameter Min
rch Receive Clock High Time 400
rcl Receive Clock Low TIme 400
rcyc Receive Clock Cycle Time 800
rds
rdh
pts
Receive Data Setup Time to
Receive Clock High (Note 1)
Receive Data Hold Time from
Receive Clock High
First Preamble Bit to Synch
(Note 2)
20
19
8
Max
1200
Units
ns
ns
ns
ns
ns
rcyc
cycles
Nole 1: All b~s entering NIC musl be properly decoded, fflhe PLL Is slill locking, Ihe clock to the NIC should be disabled orCRS delayed. Any two sequential 1 data
b~ will be Interpreted as Synch.
Note 2: This Is a minimum requirement which allows reception of a packet.
RXC\.
Serial Timing-Receive (End of Frame)
r\. /\ F~~~
- - -l '-ftcsrl tllg _I
---"'\ ~--...... )eiit~~ -J;-----rxrck ---.;
RXD::X BIT N-l X BIT N " I V'7i\ ~ _____ _
. i'
CRS ~
\ \ \ \ \ \~ r-
TLlF/9345-50
Symbol Parameter Min Max Units
rxrck
tdrb
tifg
tcrsl
Minimum Number of Receive Clocks
after CRS Low (Note 1)
Maximum of Allowed Dribble Bits/Clocks
(Note 2)
Receive Recovery Time
(Notes 4, 5)
Receive Clock to Carrier Sense Low
(Note 3)
5
3
40
0 1
rcyc
cycles
rcyc
cycles
rcyc
cycles
rcyc
cycles
Note 1: The NIC requires a minimum number of receive clocks following the deassertion of carrier sense (CRS). These additional clocks are provided by the
DP8391 SNI. If other decoder/PLLs are being used additional clocks should be provided. Short clocks or gUtches are not allowed.
Note 2: Up to 5 bits of dribble bits can be tolerated without resulting in a receive error.
Note 3: Guarantees to only load bH N, additional bits up to tdrb can be tolerated.
Note 4: This is the time required for the receive state machine to complete end of receive processing. This parameter Is not measured but Is guaranteed by design.
This is not a measured parameter but is a design requirement.
Nole 5: CRS must remain d .... erted for a minimum of 2 RXC cycles to be recognized as end of carrier.
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