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5.0 Instruction Set Overview
INTRODUCTION
Utilizing a total of only 30 basic instructions and capable of
5 basic addressing modes, the BCP's instruction set is very
easy to learn, executes extremely fast, and greatly reduces
the programming effort required in communications processing.
This is possible because the BCP is a Reduced
Instruction Set Computer; (Le., employs a RISC processor.)
The following paragraphs introduce the BCP's architecture
by discussing addressing modes and briefly discussing the
Instruction Set. For detailed explanations and examples of
each instruction, refer to the Instruction Set Reference Section.
INSTRUCTION AND DATA MEMORY
The BCP utilizes a true Harvard Architecture, where the instruction
and data memory are organized into two independent
memory banks, each with their own address and data
buses. Both the Instruction Address Bus and the Instruction
Bus are 16 bits wide with the Instruction Address Bus addressing
memory by words. (A word of memory is 16 bits
long; Le., 1 word = 2 by1es.) Most of the instructions are
one word long. The exceptions are two words long, containing
a word of instruction followed by a word of immediate
data. The combination of word sized instructions and a word
based instruction address bus eliminates the typical instruction
alignment problems faced by many CPU's.
The Data Address Bus is 16 bits wide, (with the low order 8
bits multiplexed on the Data Bus), and the Data Bus is 8 bits
wide, (Le., one byte wide). The Data Address Bus addresses
memory by bytes. Most of the BCP's instructions operate on
by1e-sized operands.
Note that although both instruction addresses and data addresses
are 16 bits long, these addresses are for two different
buses and, therefore, have two different numerical
meanings, (Le., byte address or word address.) Each instruction
determines whether the meaning of a 16-bit address
is that of an instruction word address or a data byte
address. Little confusion exists though because only the
program flow instructions interpret 16-bit addresses as instruction
addresses.
OPERAND ADDRESSING MODES
An addressing mode is the mechanism by which an instruction
accesses its operand(s). The BCP's architecture supports
five basic addressing modes: register, immediate, indexed,
immediate-relative, and register-relative. The first
two allow instructions to execute the fastest because they
require no memory access beyond instruction fetch. The
remaining three addressing modes point to data or instruction
memory. Typical of a RISC processor, most of the instructions
only support the first three addressing modes,
with one of the operands always limited to the register addressing
mode.
Register Addressing Modes
There are two terminologies for the register addressing
modes: Register and Limited Register. Instructions that allow
Register operands can access all the registers in the
CPU. Note that only 32 of the 44 CPU registers are available
at any given point in time because the lower 12 register
locations (RO-R11) access one of two switchable register
banks each. (See the "CPU Register Set" section for more
information on the CPU register banks.) Instructions that allow
the Limited Register operands can access just the first
28 registers of the CPU. Again, note that only 16 of these 28
registers are available at any given point in time. Table I
shows the notations used for the Register and Limited Register
operands. Some instructions also imply the use of certain
registers, for example the accumulators. This is noted in
the discussions of those instructions.
Immediate Addressing Modes
The two types of the immediate addressing modes available
are: Immediate numbers and Absolute numbers. Immediate
numbers are 8 bits of data, (one data by1e), that code directly
into the instruction word. Immediate numbers may represent
data, data address displacements, or relative instruction
addresses. Absolute numbers are 16-bit numbers. They
code into the second word of two word instructions and they
represent absolute instruction addresses. Table II shows
the notations used for both of these addressing modes.
TABLE I. Register Addressing Mode Notations
Notation Type of Register Operand Registers Allowed
Rs Source Register RO-R31
Rd Destination Register RO-R31
Rsd Register is both a Source & Destination RO-R31
rs Limited Source Register RO-R15
rd Limited Destination Register RO-R15
rsd Limited Register is both a Source & Destination RO-R15
TABLE II. Immediate Addressing Mode Notations
Notation Type of Immediate Operand Size
n Immediate Number 8 Bits
nn Absolute Number 16 Bits
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