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6.0 Instruction Set Reference (Continued)
CPL
Syntax
CPL
Complement
Rsd
Affected Flags
N,Z
Description
-register
Logically complements the contents of the register Rsd,
placing the result back into that register.
Example
Load the fill-bit count passed from the host into the Transmitter's
Fill-Bit Register {FBRl. R3, and then perform the
required one's complement of the fill-bit count. In this example,
register 20 contains the fill-bit count.
EXX 1,1 ;select alternate banks
MOVE R20, FBR ;Ioad {FBR)
CPL FBR ;complement fill-bit count
I nstruction Format
11 I 0 I 1 I 0 I b~~o~; I 0 I 0 I 0 I 0 I Rsd
15
T-states
2
Bus Timing
Figure 7
Operation
Rsd -+ Rsd
4 o
EXX
Syntax
EXX
Exchange Register Banks
ba, bb (,g)
Affected Flags
None
Description
Selects which CPU register banks are active by exchanging
between the main and alternate register sets for each bank.
Bank A controls RO-R3 and Bank B controls R4-R11. The
table below shows the four possible register bank configurations.
Note that deactivated registers retain their current values.
The Global Interrupt Enable bit [GIE] can be set or
cleared, if desired.
Example
Register Bank Configurations
ba bb Active Register Banks
0 0 Main A, Main B
0 1 Main A, Alternate B
1 0 Alternate A, Main B
1 1 Alternate A, Alternate B
Activate the main register set of Bank A, the alternate register
set of Bank B, and leave the Global Interrupt Enable bit
[GIE] unchanged.
EXX 0,1 ;select main A, alt B reg banks
Instruction Format
15
T-states
2
Bus Timing
Figure 7
Operation
Case ba of
0: activate main Bank A
1: activate alternate Bank A
End case
Case bb of
0: activate main Bank B
1: activate alternate Bank B
End case
Case g of
0: leave [GIE] unaffected, (default)
1 : (reserved)
2: set [GIE]
3: clear [GIE]
End case
6 -l- 4 3 2
OO-GIE not affected
01-reserved
10-SetGIE
11-Clear GIE
o
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