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4.0 Transmit/Receive Packet Encapsulation/Decapsulation (Continued) FCS FIELD the CRC generator. Packets with improper CRC will be re- The Frame Check Sequence (FCS) is a S2-bit CRC field jected. The AUTODIN II (X32 + X26 + X23 + X22 + X16 + calculated and appended to a packet during transmission to X12 + Xll + Xl0 + XS + X7 + X5 + X4 + X2 + Xl + 1) allow detection of errors when a packet is received. During reception, error free packets result in a specific pattern in Connection Diagram NC 10 NC 11 AD6 12 AD7 13 ADS 14 AD9 15 AD10 16 AD11 17 GND 18 GND 19 AD12 20 AD13 21 AD14 22 AD15 23 ADSO 24 NC 25 HC 26 Plastic Chip Carrier ~ ~ ~ Neg ~ N ~ 1",0 I~ ~ ~ ~ ~ ~ ~ ~ ~ = ~ = ~ ~ ~ ~ PCC 68 PIN polynomial is used for the CRC calculations. 60 59 58 57 56 55 54 53 52 51 46 45 44 NC NC INT RESET CD RXD CSR RXCK Vee Vee LPSK TXD TXCK TXEN BREQ NC NC TL/F/9345-5 ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADS AD9 AD10 AD11 GND AD12 AD13 AD14 AD15 MWR Dual-In-Line Package RAO RA1 RA2 RA3 PRO WACK INT RESET COL RXD CRS RXC Vee LBK TXD TXC TXE BREQ BACK PRQ/ADS1 READY PWR RACK SSCK r 5.0 Pin Descriptions BUS INTERFACE PINS Symbol ADO-AD15 ADSO DIP Pin No 1-12 14-17 18 Function I/O,Z I/O,Z Order Number DP8390CN-1 or DP8390CV-1 See NS Package Number N48A or V68A TL/F 19345-4 Description MULTIPLEXED ADDRESS/DATA BUS: • Register Access, with DMA inactive, CS low and ACK returned from NIC, pins ADO-AD? are used to read/write register data. AD8-AD15 float during I/O transfers. SRD, SWR pins are used to select direction of transfer. • Bus Master with BACK input asserted During t1 of memory cycle ADO-AD15 contain address During t2, tS, t4 ADO-AD15 contain data (word transfer mode). During t2, tS, t4 ADO-AD? contain data, AD8-AD15 contain address (byte transfer mode). Direction of transfer is indicated by NIC on MWR, MRD lines. ADDRESS STROBE 0 • Input with DMA inactive and CS low, latches RAO-RAS inputs on falling edge. If high, data present on RAO-RAS will flow through latch. • Output when Bus Master, latches address bits (Ao-A 15) to external memory during DMA transfers. 1-5?
..... o C) Q) "IS' C'I ~ Z -..... ~ ('I) co D C 5.0 Pin Descriptions (Continued) BUS INTERFACE PINS (Continued) Symbol DIP Pin No Function CS 19 I MWR 20 O,l MRD 21 O,l SWR 22 I SRD 23 I ACK 24 0 RAO-RA3 45-48 I PRO 44 0 WACK 43 I INT 42 0 RESET 41 I BREQ 31 0 BACK 30 I PRQ,ADSl 29 O,l READY 28 I Description CHIP SELECT: Chip Select places controller in slave mode for J.tP access to internal registers. Must be valid through data portion of bus cycle. RAO-RA3 are used to select the internal register. SWR and SRD select direction of data transfer. MASTER WRITE STROBE: Strobe for DMA transfers, active low during write cycles (t2, t3, tw) to buffer memory. Rising edge coincides with the presence of valid output data. TRI·STATE@ until BACK asserted. MASTER READ STROBE: Strobe for DMA transfers, active during read cycles (t2, t3, tw) to buffer memory. Input data must be valid on rising edge of MRD. TRI·STATE until BACK asserted. SLAVE WRITE STROBE: Strobe from CPU to write an internal register selected byRAO-RA3. SLAVE READ STROBE: Strobe from CPU to read an internal register selected byRAO-RA3. ACKNOWLEDGE: Active low when NIC grants access to CPU. Used to insert WAIT states to CPU until NIC is synchronized for a register read or write operation. REGISTER ADDRESS: These four pins are used to select a register to be read or written. The state of these inputs is ignored when the NIC is not in slave mode (CShigh). PORT READ: Enables data from external latch onto local bus during a memory write cycle to local memory (remote write operation). This allows asynchronous transfer of data from the system memory to local memory. WRITE ACKNOWLEDGE: Issued from system to NIC to indicate that data has been written to the external latch. The NIC will begin a write cycle to place the data in local memory. INTERRUPT: Indicates that the NIC requires CPU attention after reception transmission or completion of DMA transfers. The interrupt is cleared by writing to the ISA. <strong>Al</strong>l interrupts are maskable. RESET: Reset is active low and places the NIC in a reset mode immediately, no packets are transmitted or received by the NIC until STA bit is set. Affects Command Register, Interrupt Mask Register, Data Configuration Register and Transmit Configuration Register. The NIC will execute reset within 10 BUSK cycles. BUS REQUEST: Bus Request is an active high signal used to request the bus for DMA transfers. This Signal is automatically generated when the FIFO needs servicing. BUS ACKNOWLEDGE: Bus Acknowledge is an active high signal indicating that the CPU has granted the bus to the NIC. If immediate bus access is desired, BREQ should be tied to BACK. Tying BACK to Vee will result in a deadlock. PORT REQUEST I ADDRESS STROBE 1 • 32 BIT MODE: If LAS is set in the Data Configuration Register, this line is programmed as ADS1. It is used to strobe addresses A 16-A31 into external latches. (A16-A31 are the fixed addresses stored in RSARO, RSAR1.) ADSl will remain at TRI·STATE until BACK is received . • 16 BIT MODE: If LAS is not set in the Data Configuration Register, this line is programmed as PRQ and is used for Remote DMA Transfers. In this mode PRQ will be a standard logic output. NOTE: This line will power up as TRI-8TATE until the Data Configuration Register is programmed. READY: This pin is set high to insert wait states during a DMA transfer. The NIC will sample this Signal at t3 during DMA transfers. 1·58
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
Page 18 and 19: 5.0 Pin Descriptions (Continued) BU
Page 20 and 21: 6.0 Direct Memory Access Control (D
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Page 24 and 25: 8.0 Packet Transmission (Continued)
Page 26 and 27: 10.0 Internal Registers (Continued)
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Page 40 and 41: 12.0 Loopback Diagnostics (Continue
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Page 48 and 49: 15.0 Switching Characteristics AC S
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Page 64 and 65: AC Timing Test Conditions Input Pul
Page 66 and 67: 2.0 Block Diagram COL CRS PROTOCOL
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Page 76 and 77: 9.0 Remote DMA The Remote DMA chann
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Page 98 and 99: 15.0 Switching Characteristics AC S
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Page 114 and 115: AC Timing Test Conditions Input Pul
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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