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-----------------------------------------------------------------------,c 15.0 Switching Characteristics (Continued) BSCK ADSO T1 Walt State Insertion T2 13 TW T4 "'U Q) c.,) CD C) ~ ...... ..... z en c.,) I\) ~ ~ ..... R~~ ________ ......................... ~ TL/F/9345-44 Symbol ews ewr Parameter External Wait Setup to T3..l. Clock (Note 1) External Wait Release Time (Note 1) Min Max Units 10 ns 15 ns Nota 1: The addition of wait.tates affects the count of deserialized bytes and is limHed to a number of bus clock cycles depending on the bus clock and network rates. The allowable waH states are found in the table below. (Assumas 1 Mbitisec data rate.) BUSCK(MHz) Byte Transfer '" of Walt States Word Transfer The number of allowable wait states in byte mode can be calculated using: *W(by1emodO) - C.:::k -1) 1 0 1 #W - Number of Walt States 2 2 4 tnw - Network Clock Period !bsck - BSCK Period 4 6 9 Tha number of allowable waH states in word mode can be calculated using: 8 13 Table assumes 1 MHz network clock. 19 ( 5tnw ) #W(word modo) - 2tbsck- 1 1·95
15.0 Switching Characteristics (Continued) Remote DMA (Read, Send Command) I T1 I T2 I T3 K-J~ BSCK~~ ADSO S ~ S t.lRD \. !-t>pwrl I--bpwrh --- --- S PWR -- PRQ ~' RACK ~ ..... I- prql S~ r~ '---J -- rakw - ADO-IS ( AO-AI5 ) ( 00-015 ~ S TLlF/9345-45 Symbol Parameter Min Max Units bpwrl Bus Clock to Port Write Low 43 ns bpwrh Bus Clock to Port Write High 40 ns prqh Port Write High to Port Request High (Note 1) 30 ns prql Port Request Low from Read Acknowledge High 45 ns rakw Remote Acknowledge Read Strobe Pulse Width 20 ns Note 1: Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending. 1-96
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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Page 56 and 57: 15.0 Switching Characteristics (Con
Page 64 and 65: AC Timing Test Conditions Input Pul
Page 66 and 67: 2.0 Block Diagram COL CRS PROTOCOL
Page 68 and 69: 4.0 Transmit/Receive Packet Encapsu
Page 70 and 71: 5.0 Pin Descriptions (Continued) BU
Page 72 and 73: 7.0 Packet Reception (Continued) fo
Page 74 and 75: 7.0 Packet Reception (Continued) Er
Page 76 and 77: 9.0 Remote DMA The Remote DMA chann
Page 78 and 79: 10.0 Internal Registers (Continued)
Page 90 and 91: 11.0 Initialization Procedures (Con
Page 92 and 93: 13.0 Bus Arbitration and Timing The
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Page 96 and 97: 13.0 Bus Arbitration and Timing (Co
Page 98 and 99: 15.0 Switching Characteristics AC S
Page 114 and 115: AC Timing Test Conditions Input Pul
Page 116 and 117: 2.0 Block Diagram TRANSCEIVER CABLE
Page 118 and 119: PCC Connection Diagram 39.0. 39.0.
Page 120 and 121: 6.0 Absolute Maximum Ratings Recomm
Page 122 and 123: 9.0 Timing and Load Diagrams (Conti
Page 126 and 127: 2.0 Block Diagram COAX CABLE r ____
Page 128 and 129: ~~L ~------------------------------
Page 130 and 131: 6.0 Absolute Maximum Ratings (Note
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Page 138 and 139: I: • • • • • • Interrup
Page 140 and 141: PAL20LB Decode and DMA Interface Lo
Page 142 and 143: ~ U16/8 R1 R1,R2=4.7k.o. Note: For
Page 144 and 145: Although Cheapernet is intended for
Page 146 and 147: The transmitted packet from the SNI
Page 148 and 149: Truth Table for Various Collision D
Page 150 and 151: CHEAPERNET APPLICATION WITH THE DP8
Page 152 and 153: DP8390 Network Interface Controller
Page 154 and 155: ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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N r--------------------------------
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~ ..,. r---------------------------
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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) r--------------------------------
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Absolute Maximum Ratings (Note 1) I
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(W) r------------------------------
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M r--------------------------------
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MUX~ __________________ The BIPLAN
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U) ,-------------------------------
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~r---------------------------------
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~ .--------------------------------
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ ,--------------------------------
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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.----------------------------------
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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-----------------------------------
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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-----------------------------------
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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m . r------------------------------
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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,----------------------------------
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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,----------------------------------
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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-----------------------------------
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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-----------------------------------
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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.----------------------------------
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-----------------------------------
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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.... ~ ~ U) r----------------------
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..... U) z • U) r----------------
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.,... U) Z 3020 LPRINT USING" 1111
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. II) or- II) Z
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,.. i ~~---------------------------
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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-----------------------------------
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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