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SUPPORTING DOCUMENTS The following references can be used to obtain further information. - DP8390N-1 Data Sheet - Advanced Peripherals IEEE 802.3 Local Area Network Guide - DP8390 Data Sheet Addendum, Sept. 1987 - IEEE 802.3 1 Base5 ("StarLAN") - 82C550A Data Sheet (a product of Chips and Technology Inc.) - MK5035N Data Sheet (a product of Mostek Corporation) - PT3589 pulse transformer Data Sheet (a product of VALOR Electronics) - BH500-1436 pulse transformer Data Sheet (a product of BH Electronics) - NP5413 pulse transformer Data Sheet (a product of Nano Pulse Inc.) CONSIDERATIONS FOR USING REV. C DP8390N·1 (1) In order for the 4-byte packet header to be properly written by the DP8390, the DMA clock to Network clock may not be greater than 4:1; thus, in StarLAN applications, the DMA clock may not exceed 4 MHz. Higher bus clock speeds (up to 8 MHz), however, can be achieved by manipulating the packet header under software control. If you are using a DMA clock which is greater than 4 MHz, the DP8390 occasionally copies the Lower Byte Count into the header twice, and fails to write the Upper Byte Count. The Upper byte count, however, may be calculated by subtracting the Next Page Pointer (second byte in the header) with the Next Page Pointer of the previous packet. See DP8390 Datasheet Addendum section 3.1. (2) Due to the asynchronous nature between the local and remote DMAs, a race condition exists which may cause the local DMA to use the remote DMA's address counter or vice versa. This problem is fixed using a DMA clock synchronous to the transmit clock of the encoder, or a clock derived from the transmit clock. (3) Because of problem (1) above, the "send packet" command will not operate at bus clock frequencies above 4 MHz. Instead, use the Remote Read DMA and update BNDRY under software control. Note that there is a special consideration for updating BNDRY as specified in section 3.0 of the DP8390 Data Sheet Addendum. BNDRY must always be kept at least one 256-byte buffer behind the CURR pointer. (4) Rev. C parts will be marked as DP8390N-1 and will oper· ate at a maximum bus clock of 8 MHz. DAUGHTER CARD PARTS LIST Resistors Capacitors Inductors 1200 (R3) 1 5600 (R4) 1 2.2 KO (R1, 2) 2 10 MO (R7 or R8) 1 30pF (C3) 1 15 pF (C7, 8 or 15,16) 2 0.1 ,..F (C1 , 2) 2 35,..F (C11) 1 40,..H (L1) DAUGHTER CARD PARTS LIST (Continued) Crystal 8 MHz (for MK5035N) NDKAT-51 16 MHz (for 82C550A) NDKAT-51 ICs and Other DS8923 (U2) MM74HC74 (U1) MM74HC04 (U7) Manchester ENDECs 82C550A (U6) MK5035N Pulse Transformers PT3589 NP5413 BH500-1436 LIST OF OTHER MANUFACTURERS MANCHESTER ENCODER/DECODERS 82C550A Chips and Technologies Ken Buntaran, Technical Marketing Engineer 521 Cottonwood Drive Milpitas, CA 95035 (408) 434-0600 MK5035N Mostek Corporation 1310 Electronics Drive Carrollton, TX 75006 (214) 466-6000 PULSE TRANSFORMERS BH Electronics John DeCramer, Engineering Manager 604 Michigan Road Marshall, MN 56258 (507) 532-3211 Nano Pulse Industries, Inc. 440 Nibus Street P.O. Box 9398 Brea, CA 92621 (714) 529-2600 Pulse Engineering, Inc. Rey Bautista, DeSign Engineer 7250 Convoy Court San Diego, CA 92111 (619) 268-2449 VALOR Electronics, Inc. Ernest R. Jensen, Product Development 6750 Nancy Ridge Drive San Diego, CA 92121 (619) 458-1471 PHONE JACK Nova-Tronic, Inc. Jeff Hines, Sales Manager 4701 Patrick Henry Drive #24 Santa Clara, CA 95054 (408) 727·9530 CRYSTALS NDK·America 20300 Stevens Creek Blvd. Cupertino, CA 95014 (408) 255-0831 1-151
AN·498 "fnn Pulse Transformer U3 .----- , 10 RX+ , RX- , Jl/21 , B ""n , • I , 14 , Jl/13 , ~I TX+ , ._--- TX-, 3 12 __ • +5V StarLAN Front End Using the MK5035N RECEIVER/ ENCODER/ DRIVER DECODER DSB923 MK5035N U2 +5V U5 20·vee ~ i . 5 1Re 4 1RD ~~~!~;-LEN---4------------118 XEN ._ 19 ~ 13' , C7 XD .. ~ h _____ fe' ! 15(F ' , 14 IXI RJ-45 Modular Jack BCd RX+ 3 RX- 6 TX+l TX- 2 ( , , ' '-IX2 CB 15pF Vee14. GND71 ,. -, RENA 6 CLSN 7 eMODE iL5V 3 CRS 1 COL SNI SOCKET Jl XSEL Lov RX+· 22 XeLSN £5V LBACK .L 5V RX_· 21 TCLK 16 TENA 15 TX 17 RX9 RCLK B RESET 11 GND· 10 11 TXC 12 TXE 10 TXD 2 RXD 4 RXC 16 RST PROVIDES A 4 MHz SYNCHRONOUS BUS CLOCK FOR THE DPB390. REQUIRED FOR REV e, BUT 19 35}'F !I~ NOT FOR DPB390BN. B Cll lx1 TLiF 19346-4
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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15.0 Switching Characteristics AC S
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Page 116 and 117: 2.0 Block Diagram TRANSCEIVER CABLE
Page 118 and 119: PCC Connection Diagram 39.0. 39.0.
Page 120 and 121: 6.0 Absolute Maximum Ratings Recomm
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Page 148 and 149: Truth Table for Various Collision D
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Page 160 and 161: StarLAN With The DP839EB Evaluation
Page 164 and 165: Pulse Transformer U3 .----. j " "P>
Page 166: ELECTROSTATIC DISCHARGE TEST (ESD)
Page 169 and 170: Section 2 Contents DP8340INS32440 I
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Page 175 and 176: Timing Characteristics Oscillator F
Page 177 and 178: Timing Waveforms (Continued) TA REG
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Page 181 and 182: Detailed Functional Pin Description
Page 183 and 184: Message Format (Continued) DATA REC
Page 185 and 186: Timing Characteristics (Notes 2, 6,
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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4.0 Electrical Specifications (Cont
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5.0 Instruction Set Overview (Conti
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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4.0 Timing Waveforms (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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