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RECEIVER INTERRUPT The receiver interrupt algorithm handles any or all seven addresses possible on the twinax line. The same code is used for each address by utilizing a page oriented memory scheme. Session specific variables are stored in memory pages of 256 bytes each. All session control pages, or SCPs are on 256-byte even boundaries. By setting the high order byte of a BCP index register to point to a particular page or SCP, the low order byte then references an offset within that page. Setting up data memory in such a way that the first SCP begins at an address of B #xxxx xOOO 0000 0000 further enhances the usefulness of this construct. In this scheme, the high byte of the SCP base pointer can be used to set the particular SCP merely by summing the received or selected address into the lower three bits of the base register. NORMAL OPERATION In normal operation, the configuration described thus far is used in the following manner: After initializing the registers, data structures are initialized, and interrupt routines should be activated. This application utilizes the receiver, transmitter, timer, and bi-directional interrupts. Since (I BR) is set to H # 1 F, the interrupt table is located at H # 1 FOO. A LJMP to the receiver interrupt routine should be installed at location H # 1 F1 04, the transmitter interrupt vector at H # 1 F08, the BIRO interrupt vector at H # 1 F1 0, and the Timer interrupt vector at H # 1 F14. Un-masking the receiver interrupt and BIRO at start up allows the device to come on-line. When interrupt by the receiver, the receiver interrupt service routine first checks the [ERR) flag in (TSR [B5]). If no errors have been flagged, the received_EOM flag is either set or cleared. This is accomplished by comparing (TSR [BO-2]) with the B # 111 EOM delimiter. A test of the selected flag, (GP5' [B7)) determines if any of the active addresses are selected. Assuming that the system is just coming on line, none of the devices would be selected. If the frame is addressed to an active device, the SCP for that device is set, and the command is parsed. Parsing the command sets the appropriate state flags, so that upon exiting, the interrupt routine will be prepared for the next frame. Once parsed, the command can be further decoded and handled. If the command is queue-able, the command is pushed on the internal command queue, and the receiver interrupt routine exits. If the command requires an immediate response, then the response is formulated, the timer interrupt is setup, and the routine is exited. The timer interrupt is used in responding to the host by waiting an appropriate time to invoke the transmit routine. The typical response delay is 45 ± 15 ,""S after the last valid fill bit received in the command frame. Some printers and terminals are allowed a full 60 ± 20 '""S to respond. In either case, simply looping is very inefficient. The immediate response routine simply sets the timer for the appropriate delay and unmasks the timer. In the transmit routine, the data to be sent is referenced by a pointer and an associated count. The routine loads the appropriate address in the three LSBs of (TCR), and writes the data to be sent into (RTR). This starts the transmitter. If the data count is greater than the transmit FIFO depth (three bytes), the Transmit FIFO Empty interrupt [TFE) is setup. This vectors to code that refills the FI FO and re-enabies that interrupt again, if needed. This operation must be carried out before the transmitter is finished the last frame in the FIFO or the message will end prematurely. The last frame transmitted must contain the EOM delimiter. It can be loaded into (TCR) and data into (RTR) while the transmitter is running without affecting the current frame. In other words, the transmit FIFO is 12 bits wide, including address and parity with data; the address field is clocked along with the data field. In this way, multi-byte response may be made in efficient manner. ERROR HANDLING In 5250 environments, the time immediately after the end of message is most susceptible to transmission errors. The BCP's receiver does not detect an error after the end of a message unless transitions on the line continue for a complete frame time or resemble a valid sync bit of a multiframe transmission. If the twinax line is still active at the end of what could be an error frame, the receiver posts the LMBT error. For example, if noise on the twinax line continues for up to 11 ,""S after the three required fill bits, the receiver will reset without flagging an error. If noise resembles a start bit, the receiver now expects a new frame and will post an error if a loss of synchronization occurs. If the noisy environment is such that transitions on the receiver's input continue for 11 "'S, or the receiver really has lost sync on a real frame, the error is posted. Basically, the receiver samples [LA) in addition to the loss of synchronization indication to determine when to reset or to post an error. After a loss of synchronization in the fill bit portion of a frame, if the [LA) flag's time-out of 2 '""S is reached prior to the end of what could be the next frame, the receiver will reset. If the transitions prevent [LA) from timing out for an entire 11 '""S frame time, a LMBT error is posted. This method for resetting the receiver is superior in that not only are the spurious loss of mid bit errors eliminated, the receiver performs better in noisy environments than other designs. SUMMARY The IBM 5250 twinax environment is less understood and in some ways more complex than the 3270 environment to many developers. This application note has attempted to explain some basics about twinax as a transmission medium, the hardware necessary to interface the DP8344 to that medium, and some of the features of the BCP that make that task easier. Schematics are included in this document to illustrate possible designs. Details of the twinax waveforms were discussed and figures included to illustrate some of the more relevant features. Also, some different software approaches to handling the transceiver interface were discussed. REFERENCES 5250 Information Display to Systeml36 and Systeml38 System Units Product Attachment Information, IBM, November 1986. Transmission Line Characteristics, Bill Fowler, National Semiconductor Application Note AN-108. Basic Electromagnetic Theory, D.T. Paris, F.K. Hurd McGraw-Hili Inc., 1969. l: z I U1 .... G) 2·211
~r-----------------------------------------------------------------------. .... I.t) APPENDIX A: EXAMPLE CODE z • cc The following code was assembled with the HILEVEL assembler. Table II shows the correlation between HILEVEL mnemonics and the mnemonics used in National data sheets for the DP8344V. HILEVEL TABLE II National Semiconductor MOVE Rs,Rd LD Ptr ,Rd{ ,Mde} ST Rs,Ptr{,Mde} LDAX Ptr,Rd STAX Rs,Ptr LDNZ n,Rd STNZ Rs,n LDI n,Rd STl n,Ptr ADD Rs,Rd ADDRI Rs,Ptr{,Mde} ADDI n,Rsd ADC Rs,Rd ADCRI Rs,Ptr{,Mde} SUBT Rs,Rd SUBRI Rs,Ptr{,Mde} SUBI n,Rsd SBC Rs,Rd SBCRI Rs,Ptr{,Mde} AND Rs,Rd ANDRI Rs,Ptr{,Mde} ANDI n,Rsd OR Rs,Rd ORRI Rs,Ptr{ ,Mde} oRI n,Rsd XOR Rs,Rd XORRI Rs,Ptr{,Mde} XORI n,Rsd CMP CF'L BIT SRL SLA ROT Rs,n Rsd Rs,n Rsd,n Rsd,n Rsd,n 110VE Rs,Rd MOVE EmIr J, Rd MOVE Rs, EmIrJ MOVE EIr + AJ,Rd MOVE Rs,EIr + AJ MOVE [IZ + nJ ,rd MOVE rs,EIZ + nJ MOVE n,rd MOVE n,ElrJ ADDA Rs,Rd ADDA Rs, emir· J ADD n,rsd ADCA F
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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PCC Connection Diagram 39.0. 39.0.
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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#3/30/B7••••• D2APPS.ASM
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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Applications Information (Continued
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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Functional Description (Continued)
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Electrical Characteristics unless o
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Functional Description* (Continued)
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TABLE III. Remote Digital Loopback
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Section 7 Physical Dimensions
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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