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6.0 Instruction Set Reference
INTRODUCTION
The Instruction Set Reference section contains detailed information
on the syntax and operation of each BCP instruction.
The instructions are arranged in alphabetical order by
mnemonic for easy access. Although this section is primarily
intended as a reference for the assembly language programmer,
previous assembly language experience is not a
prerequisite. The intent of this instruction set reference is to
include all the pertinent information regarding each instruction
on the pagels) describing that instruction. The only exceptions
to this rule concerns the instruction addressing
modes and the bus timing diagrams. The discussion of the
instruction addressing modes occurs at the beginning of the
BCP Instruction Set Overview section and, therefore, will
not be repeated here. The figures for the bus timing diagrams
are located at the end of this introduction rather than
constantly repeating them under each instruction. On the
other hand, the information that is contained under each
instruction is divided into eight categories titled: Syntax, Affected
Flags, Description, Example, Instruction Format,
T-states, Bus Timing, and Operation. The following paragraphs
explain what information each category conveys and
any special nomenclature that a category may use.
Syntax
This category illustrates the assembler syntax for each instruction.
Multiple lines are used when a given instruction
supports more than one type of addressing mode or if it has
an optional mnemonic. All capital letters, commas, (,) math
symbols (+, -), and brackets ([ I) are entered into the assembler
exactly as shown. Braces ({ )) surround an instruction's
optional operands and their associated syntax. The
text between the braces may either be entered in with or
omitted from the instruction. The braces themselves should
not be entered into the assembler because they are not part
of the assembler syntax. Lower case characters and operands
that begin with the capital R represent symbols. These
must be replaced with actual register names, numbers, or
equated registers and numbers. Table XXII lists all the symbols
and their associated meanings.
Affected Flags
If an instruction sets or clears any of the ALU flags, (Le.,
Negative [Nl, Zero [Zl, Carry [Cl, and/or Overflow [Vl, then
those flags affected are listed under this category.
Description
The Description category contains a verbal discussion
about the operation of an instruction, the operands it allows,
and any notes highlighting special considerations the prorammer
should keep in mind when using the instruction.
Example
Each instruction has one or more coding examples designed
to show its typical usage(s). For clarity, register
name abbreviations are often used instead of the register
numbers, (Le., RTR is used in place of R4). Each example
assumes that the ".EQU" assembler directive has been previously
executed to establish these relationships. Information
relating register abbreviations to register names, numbers,
and purpose is located in the CPU Registers section.
Instruction Format
This category illustrates the formation of an instruction's
machine code for each operand variation. Assembly or disassembly
of any instruction can be accomplished using
these figures.
T-states
The T -state category lists the number of CPU clock cycles
required for each instruction, including operand variations
and conditional considerations. Using this information, actual
execution times may be calculated. For example, if the
conditional relative jump instruction's condition is not met,
the CPU's clock cycle is 18.867 MHz ([CCS] = 0), and no
instruction wait states are requested ([IW1-0] =00), then
Jcc's execution time is calculated as shown below:
texecution
~ 1 /(CPU clock frequency) • T-states
= 1/(18.867*106 Hz) * 2
= (53*10-9s) * 2
= 106 ns
See the section BCP Timing for more information on calculating
instruction execution times.
Bus Timing
This category refers the user to the Bus Timing Figures 7 to
12 on the following pages. These figures illustrate the relationship
between software instruction execution and some
of the BCP's hardware signals.
Operation
The operation category illustrates each instruction's operation
in a symbolic coding format. Most of the operand
names used in this format come directly from each instruction's
syntax. The exceptions to this rule deal with implied
operands. Instructions that imply the use of the accumulators
use the name "accumulator" as an operand. Instructions
that manipulate the Program Counter use the symbol
"PC". Instructions that "push" onto or "pop" off of the internal
Address Stack specify "Address Stack" as an operand.
Instructions that save or restore the ALU flags and the register
bank selections use those terms as operands. Two
specialized operator symbols are used in the symbolic coding
format, the arrow" -- " and the concatenation operator
"&". The arrow indicates the movement of data from one
operand to another. For instance, after the operation
"Rs -- Rd" is performed the content of Rd has been replaced
with the content of Rs. The concatenation operator
"&" simply indicates that the operands surrounding an "&"
are attached together forming one new operand. For example,
"PC & [GIE] 7 ALU flags & register bank
selections -- Address Stack" means that the Program
Counter, the Global Interrupt Enable bit, the ALU flags and
the register bank selections are combined into one operand
and pushed onto the internal Address Stack. Three conditional
structures are utilized in the symbolic coding format:
the "Two Line If" structure, the "Blocked If" structure, and
the "Blocked Case" structure. Figure 4 shows the "Two
Line If" structure. If the condition is met then the operation
is performed, otherwise the operation is not performed.
If condition
then operation
FIGURE 4. Two Line If Structure
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