~ National ~ Semiconductor - Al Kossow's Bitsavers

7.0 CPU Registers (Continued)
BIRO - Bi-directional Interrupt ReQuest '" [Read
only]. Reflects the logic level of the Bi-directional
interrupt pin (BIRO). Updated at the beginning of
each instruction cycle.
7 6 5 4 3 2 o
I TO I RR I RW I BIRQ I N I v I C I z I
N
v
C
z
DCR
- Negative ... A high level indicates a negative
result generated by an arithmetic, logical or shift
instruction.
- OVerflOW ... A high level indicates an overflow
condition generated by an arithmetic instruction.
- Carry ... A high level indicates a carry or borrow
generated by an arithmetic instruction. During a
shift/rotate operation the state of the last bit shifted
out appears in this location.
- Zero ... A high level indicates a zero result generated
by an arithmetic, logical or shift instruction.
DEVICE CONTROL REGISTER
[Alternate RO; read/write]
ecs - CPU Clock Select .,. Selects CPU clock frequency.
OCLK represents the frequency of the
on-chip oscillator, or the externally applied clock
on input X1.
CCS
o
CPU Clock
OCLK
1 OCLK/2
TCS1,O- Transceiver Clock Select ... Selects transceiver
clock, TCLK, frequency.
OCLK represents the frequency of the on-chip
oscillator, or the externally applied clock on input
X1. X-TCLK is the external transceiver clock input.
765 43210
I ccs I TCS1 ! TCSO ! IW1 I IWO ! DW2 I DW1 ! DWO!
TCSt,a
TCLK
00 OCLK
01 OCLK/2
10 OCLK/4
11 X-TCLK
IW1,O - Instruction memory Wait-state select ...
Selects from 0 to 3 wait states for accessing
instruction memory.
DW2-0 -
DS DATA STACK
[Main R31; read/write]
Data memory Walt-state select ... Selects
from 0 to 7 wait states for accessing data memory.
D87-0 - Data Stack ... Data stack input/output port.
Stack is 16 bytes deep. Further information:
Chapter CPU.
7 654 321 0
I DS7 I DS6 I DS5 I DS4 I DS3 ! DS2 ! DS1 I DSO !
ECR ERROR CODE REGISTER
[Alternate R4 with SEC high; read only]
OVF - Receiver OVerFlow ... Set when the receiver
has processed 3 words and another complete
frame is received before the FIFO is read by
the CPU. Cleared by reading IECR} or by asserting
[TRES].
PAR - PARity error ... Set when bad (odd) overall
word parity is detected in any receive frame.
Cleared by reading I ECR} or by asserting
[TRES].
IES - Invalid Ending Sequence .. , Set when the
"mini-code violation" is not detected at the appropriate
time during a 3270, 3299, or 8-bit
ending sequence. Cleared by reading I ECR}
or by asserting [TRES].
7
6 5 4 3 2 1 0
I rsv I rsv I rsv I OVF I PAR ! IES ! LMBT ! RDIS !
LMBT - Loss of Mid-Bit Transition ... Set when the
expected Manchester Code mid-bit transition
does not occur within the allowed window.
Cleared by reading I ECR} or by asserting
[TRES].
RDIS - Receiver DISabled while active ... Set when
transmitter is activated while receiver is active,
without RPEN being asserted. Cleared by reading
IECR} or by asserting [TRES].
FBR FILL-BIT REGISTER
[Alternate R3; read/write]
FB7-0 - Fill Bits ... 5250 fill-bit control. Further information:
Transceiver Section.
7 6 5 4 321 0
I FB7 I FB6 ! FB5 I FB4 I FB3 ! FB2 ! FB1 I FBO I
IBR INTERRUPT BASE REGISTER
[Alternate R1; read/write]
IV15-8 -
Interrupt Vector ... High byte of interrupt and
trap vectors. Further information: Chapter CPU.
7 6 543 2 1 0
I IV15 I IV14!IV131 IV12!IV11 IIV10! IV9 I IV8 I
I I I I I I I I I I I I I I I I I
. IBR 0 0 vector address .
15 8 5 o
Interrupt Vector
The interrupt vector is obtained by concatenating {lBR}
with the vector address:
Interrupt Vector Address Priority
NMI 011100 -
Receiver 000100 1 high
Transmitter 001000 2 t
Line Turn Around 001100 3
Bi-directional 010000 4
"'-
Timer 010100 5 low
rsv ... state is undefined at all times.
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