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'?'A National ~ Semiconductor ,..,A212AT 1200/300 bps Full Duplex Modem General Description The /LA212AT single-chip modem IC performs all signal processing functions required for a Bell 212A1103 compatible modem. Handshaking protocols, and mode control functions are provided by a general purpose single-chip /LC. The /LA212AT and /LC, along with several components to handle the control and telephone line interfaces, provide a high performance, cost-effective solution for an intelligent Bell 212A-compatible modem design. The modem chip performs the modulation, demodulation, filtering and certain control and self-test functions required for a Bell 212A-compatible modem, as well as additional functional enhancements. Switched capacitor filters provide channel isolation, spectral shaping and fixed compromise equalization for both high and low speed modes. A novel switched-capacitor modulator and a digital coherent demodulator provide 1200 bps QPSK operation while a separate digital FSK modulator and demodulator handle the 0-300 bps requirement. The /LA212AT includes an integral DTMF tone generator on-Chip. The receive filter and energy detector may be configured for call progress tone detection (dialtone, busy, ringback, voice), providing the front end for a smart dialer. The /LA212AT is fabricated in an advanced Double-Poly Silicon-Gate CMOS process. Features • Functions as a 212A and 103 compatible modem • Performs all signal processing functions • Interfaces to single chip /LC which handles handshaking protocols and mode control functions • DTMF tone generation • Pin and firmware compatible with the /LA212A (without integral DTMF) for easy upgrade • Call progress tone detection for smart dialer applications • On chip oscillator uses standard 3.6864 MHz crystal • Few external components required • Operates from + 5V and - 5V supplies • Low operating power: 35 mW typical • 28-lead ceramic DIP, 28-lead plastic DIP, and 28-lead surface mount packages • /LA212AT designer's kit is available Connection Diagram 28-LeadDIP "-...../ SUII- 1 28 ~VDD UII- 2 27 ~Vss RXIN- 3 26 ~AGND 001- 4 25 ~TXO ETC-5 24 r-o(i.. SYNC- 6 23 r-TXSQ EDET- 7 22 r-SCT HS- 8 21 r-IiODl SCRII- 9 20 r-IIOD2 TXD- 10 19 ~TEST XTL2- 11 18 ~DGND XTLl- 12 17 ~HSK2 SCR- 13 16~HSKI RXD- 14 15 r-RlST 'Molded Dual-In-Llne Package Order Number /LA212ATQC See NS Package Number V28A 'Ceramlc Dual-In-Llne Package Order Number /LA212ATDC See NS Package Number F28B Top View TL/H/9430-1 28-Lead PLCC (Pin numbers same as 28-lead DIp) Order Number /LA212ATDC, /LA212ATQC See NS Package Number N28B "For moS1 current pacl
Absolute Maximum Ratings* If Military/Aerospace specified devices are required, 'Note: Stresses greater than those listed under ''Absolute contact the National Semiconductor Sales Office/ Maximum Ratings" may cause permanent damage to the Distributors for availability and specifications. device. This is a stress rating only and functional operation VDD to DGND or AGND +7.0V of the device at these or any other conditions above those indicated in the operational sections of this specification is Vss to DGND or AGND -7.0V not implied. Exposure to absolute maximum rating condi- Voltage at Any Input VDD +0.3Vto tions for extended periods may affect device reliability. Vss -0.3V Voltage at Any Digital Output Voltage at Any Analog Output Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 seconds) VDD +0.3Vto DGND -0.3V VDD +0.3Vto Vss -0.3V O'Cto 70'C -65'Cto + 150'C 300'C Electrical Characteristics unless otherwise noted: VDD = 5.0V, Vss = -5.0V, DGND = AGND = OV, TA = 25'C; all digital signals are referenced to DGND, all analog signals are referenced to AGND ENERGY DETECTOR Symbol Parameter Conditions Min Typ Max Units Data Mode Vlhon OFF/ON Threshold Voltage Level at RXIN 6.5 mVrms Vlhoff ON/OFF Threshold Pin In Data Mode 5.2 ton Energy Detect Time At EDET Pin 105 155 205 ms toll Loss of Energy Detect Time 10 17 24 ms Dialer Mode Vlhon OFF/ON Threshold (Dialtone) Voltage Level at RXIN 10 mVrms Vlhon ON/OFF Threshold (Busy/Ringback) Pin In Dialer Mode 4.6 ton Energy Detect in the Dialer Mode AtEDETPin 25 30 35 ms (Detecting Call Progress Tones) Ioff Energy Detect in the Dialer Mode 30 36 42 ms (Detecting Call Progress Tones) ANALOG LINE INTERFACE Symbol Parameter Conditions Min Typ Max Units Vline (Note 1) Output Level at TXO: Data Mode 0.66 0.71 0.76 Vrms V lonh (Note 1) Output Level at TXO: DTMF HIGH Group 1.02 1.1 1.18 Vrms Vlonl (Note 1) Output Level at TXO: DTMF LOW Group 0.84 0.9 0.97 Vrms VrXSQ Output Level at TXO: TXSQ Active 0.3 mVrms Pext Extraneous Frequency Output Relative to Any DTMF Digit DTMFpower -20 dB Voo Output Offset AtTXO 5.0 mV VRXIN Talker Echo and Received Signal At RXIN 1.56 VPEAK ZRXIN Input Impedance 100 kO Note 1: Output level at TXO will vary directly with VDD supply. CLOCK INTERFACE Symbol Parameter Conditions Min Typ Max Units Fclock Clock Frequency 3.6864 MHz Tclock Clock Frequency Tolerance -.01 +.01 % Vexth External Clock Input HIGH XTAL2 Driven and XTL 1 4.5 V Grounded Vextl External Clock Input LOW 0.5 V 5-28
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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Page 508 and 509: 6.0 Connection Diagrams Dual-In-Lln
Page 510 and 511: 8.0 Block Diagram CPU INTERFACE INT
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Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
Page 521 and 522: Absolute Maximum Ratings (Notes 1 &
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Page 525 and 526: Applications Information (Continued
Page 527 and 528: Absolute Maximum Ratings (Notes 1 &
Page 529 and 530: Description of Pin Functions Pin No
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Page 535 and 536: Electrical Characteristics Unless o
Page 537 and 538: C'I 5 Pin Descriptions (Continued)
Page 539 and 540: IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
Page 541 and 542: Functional Description (Continued)
Page 543: Functional Description (Continued)
Page 547 and 548: Electrical Characteristics unless o
Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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Page 570 and 571: Section 6 Transmission Line Drivers
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Page 584 and 585: ~National ~ Semiconductor PRELIMINA
Page 586 and 587: ~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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