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AC Electrical Characteristics Unless otherwise specified, all specifications apply to the MM74HC943 over the range -40'C to +85'C using a Vee of +5V ± 10%, and a 3.579 MHz ± 0.1 % crystal.· Symbol Parameter Conditions Min Typ Max Units TRANSMITTER FeE Carrier Frequency Error 4 Hz Power Output Vee=5.0V RL = 1.2 kO I RTLA = 54900 -12 -10.5 -9 dBm 2nd Harmonic Energy RTLA = 54900 -62 -56 dBm RECEIVE FILTER AND HYBRID Hybrid Input Impedance 50 kO (Pins 15 and 16) FTLC Output Impedance 5 10 50 kO Adjacent Channel Rejection RXA2=GNDA, TXD=GND or Vee 60 dB Input to RXA 1 DEMODULATOR (INCORPORATING HYBRID, RECEIVE FILTER AND DISCRIMINATOR) Carrier Amplitude -48 -12 dBm Bit Jitter SNR = 30dB Input = - 38 dBm Baud Rate = 300 Baud } 100 200 ",S Bit Bias <strong>Al</strong>ternating 1-0 Pattern 5 10 % Carrier Detect Trip Points CDA=1.2V I Off to On -45 -42 -40 dBm Vee=5.0V I On to Off -47 -45 -42 dBm Carrier Detect Hystereisis Vee=5.0V 2 3 4 dB AC Specification Circuit SUPPLIES Vee = + 5V 3.5795 MHz ± 0.1 % rD~ RTLA 2.2k Vee TLA GNDA - TXA -RXA2 22k -L -L 1 00 .F"JI .F 600 MM74HC943 ~ "::" "::" TEST TXO +-- DATA INPUT OUTPUT + ~ RXAI RXO _ DATA OUTPUT TEST COT COA FTLC INPUT r~ 'V "::" -LO.lI'F -L0.1•F -L0.1• F ±10% +5V T T L GNOA TL/F/5349-3 5-11
Description of Pin Functions Pin No. Name Function 1 DSI Driver Summing Input: This input may be used to transmit externally generated tones such as dual tone multifrequency (DTMF) dialing signals. 2 ALB Analog Loop Back: A logic high on this pin causes the modulator output to be connected to the demodulator input so that data is looped back through the entire chip. This is used as a chip self test. If ALB and SaT are simultaneously held high the chip powers down. 3 CD Carrier Detect: This pin goes to a logic low when carrier is sensed by the carrier detect circuit. 4 CDT Carrier Detect Timing: A capacitor on this pin sets the time interval that the carrier must be present before the CD goes low. 5 RXD Received Data: This is the data output pin. 6 Vee Positive Supply Pin: A + 5V supply is recommended. 7 CDA Carrier Detect Adjust: This is used for adjustment of the carrier detect threshold. Carrier detect hysteresis is set at 3 dB. 8 XTALD Crystal Drive: XTALD and XTALS connect to a 3.5795 MHz crystal to generate a crystal locked clock for the chip. If an external circuit requires this clock XT ALD should be sensed. If a suitable clock is already available in the system. XT ALD can be driven. 9 XTALS Crystal Sense: Refer to pin 8 for details. 10 FTLC Filter Test! Limiter Capacitor: This is connected to a high impedance output of the receiver filter. It may thus be used to evalu- Functional Description INTRODUCTION A modem is a device for transmitting and receiving serial data over a narrow bandwidth communication channel. The MM74HC943 uses frequency shift keying (FSK) of audio frequency tone. The tone may be transmitted over the switched telephone network and other voice grade channels. The MM74HC943 is also capable of demodulating FSK signals. By suitable tone allocation and considerable signal processing the MM74HC943 is capable of transmitting and receiving data Simultaneously. The tone allocation used by the MM74HC943 and other Bell 103 compatible modems is shown in Table I. The terms "originate" and "answer" which define the frequency allocation come from use with telephones. The modem on the end of the line which initiates the call is called the originate modem. The other modem is the answer modem. Data TABLE I. Bell 103 Tone <strong>Al</strong>location Originate Modem Answer Modem Transmit Receive Transmit Receive Space 1070Hz 2025Hz 2025Hz 1070Hz Mark 1270Hz 2225Hz 2225Hz 1270Hz Pin No. Name Function ate filter performance. This pin may also be driven to evaluate the demodulator. RXA 1 and RXA2 must be grounded during this test. For normal modem operation FTLC is AC grounded via a 0.1 ftF bypass capacitor. 11 TXD Transmitted Data: This is the data input. 12 GND Ground: This defines the chip OV. 13 O/Ii. Originate/Answer mode select: When logic high this pin selects the originate mode of operation. 14 SaT Squelch Transmitter: This disables the modulator when held high. The EXI input remains active. If SaT and ALB are simulta· neously held high the chip powers down. 15 RXA2 Receive Analog # 2: RXA2 and RXA 1 are analog inputs. When connected as recommended they produce a 600n hybrid. 16 RXA 1 Receive Analog # 1: See RXA2 for details. 17 TXA Transmit Analog: This is the output of the line driver. 18 EXI External Input: This is a high impedance input to the line driver. This input may be used to transmit externally generated tones. When not used for this purpose it should be grounded to GNDA. 19 GNDA Analog Ground: Analog signals within the chip are referred to this pin. 20 TLA Transmit Level Adjust: A resistor from this pin to Vee sets the transmit level. THE LINE INTERFACE The line interface section performs two to four wire conversion and provides impedance matching between the modem and the phone line. THE LINE DRIVER The line driver is a power amplifier for driving the line. If the modem is operating as an originate modem, the second harmonics of the transmitted tones fall close to the frequencies of the received tones and degrade the received Signal to noise ratio (SNR). The line driver must thus produce low second harmonic distortion. THE HYBRID The voltage on the telephone line is the sum of the transmitted and received Signals. The hybrid subtracts the transmitted voltage from the voltage on the telephone line. If the telephone line was matched to the hybrid impedance, the output of the hybrid would be only the received signal. This rarely happens because telephone line characteristic impedances vary considerably. The hybrid output is thus a mixture of transmitted and received signals. 5·12
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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12.0 Loopback Diagnostics (Continue
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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Page 480 and 481: holdloop: nop # br hold loop # # #*
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Page 490 and 491: A Comparison of the I NS8250, NS 16
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Page 494 and 495: cessed (see Figure 4), The output o
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Page 508 and 509: 6.0 Connection Diagrams Dual-In-Lln
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Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
Page 521 and 522: Absolute Maximum Ratings (Notes 1 &
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Page 525 and 526: Applications Information (Continued
Page 527: Absolute Maximum Ratings (Notes 1 &
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Page 535 and 536: Electrical Characteristics Unless o
Page 537 and 538: C'I 5 Pin Descriptions (Continued)
Page 539 and 540: IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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