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~ National ~ Semiconductor - Al Kossow's Bitsavers

~ National ~ Semiconductor - Al Kossow's Bitsavers

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7.0 CPU Registers (Continued)<br />

BIT DEFINITION TABLE (Continued)<br />

The following tables describe the location and function of all control and status bits in the various BCP addressable special<br />

function registers. The Remote Interface Configuration register {RICl. which is addressable only by a remote system, is not<br />

included.<br />

CPU (for further information See Chapter on the CPU) (Continued)<br />

Bit Name Location Reset State Function<br />

Timer TLD Timer LoaD ACR [6] a Set high, to load timer. Cleared automatically when load<br />

complete.<br />

TM15-8 Timer TRH [7-0] XXXXXXXX Input/output port of high by1e of timer.<br />

TM7-0 Timer TRL [7-0] XXXXXXXX Input/output port of low byte of timer.<br />

TMC Timer Clock ACR [5] a Selects timer clock frequency. Must not be written when<br />

Select<br />

[TST] high. Can be written at same time as [TST] and<br />

[TLD].<br />

TMC Timer Clock<br />

a CPU-CLK/16<br />

1 CPU-CLK/2<br />

TO Time Out Flag CCR [7] a Set high when timer counts to zero. Cleared by writing a 1 to<br />

[TO] or by stopping the timer (by writing a a to [TST]).<br />

TST Timer StarT ACR [7] a When high, timer is enabled and will count down from its<br />

current value. Timer is stopped by writing a a to this location.<br />

TRANSCEIVER<br />

Table includes control and status bits only. It does not include definitions of bit fields provided for the formatting (de-formatting)<br />

data frames. For further information see the Transceiver Section.<br />

Bit Name Location Reset State Function<br />

Transceiver LOOP Internal TMR [6] a When high, TX-ACT is disabled (held at 0) and transmitter<br />

Control LOOP-back serial data is internally directed to the receiver serial data<br />

input.<br />

PS2-0 Protocol Select TMR [2-0] 000 Selects protocol for both transmitter and receiver.<br />

PS2-0<br />

Protocol<br />

000 3270<br />

001 3299 Multiplexer<br />

010 3299 Controller<br />

011 3299 Repeater<br />

100 5250<br />

101 5250 Promiscuous<br />

1 1 a 8-bit<br />

111 8-bit Promiscuous<br />

RTF7-0 Receive/Transmit RTR [7-0] XXXXXXXX Input/output port of the least significant 8 bits of receive and<br />

FIFOs<br />

transmit FIFOs. [OWPl, [TF10-8] and [RTF1-0] are pushed<br />

onto the transmit FIFO on moves to {RTR I. [RF10-8] and<br />

[RTF7-0] are popped from receive FIFO on moves out of<br />

{RTRI.<br />

2-139

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