~ National ~ Semiconductor - Al Kossow's Bitsavers

9.0 Remote Interface Reference
REMOTE INTERFACE CONFIGURATION REGISTER
This register can be accessed only by the remote system.
To do this, CMD and RAE must be asserted and the [LOR]
bit in the ACR register must be low.
SIS
SS
FW
LR
LW
76543210
I BIS I SS I FW I LR I LW I STRT I MS1 I MSO I RIC
STRT
Bidirectional Interrupt Status ... Mirrors the state
of 1M3 (lCR bit 3), enabling the remote system to
poll and determine the status of the BIRO 110.
When BIRO is an output, the remote system can
change the state of this output by writing a one to
BIS. This can be used as an interrupt acknowledge,
whenever BIRO is used as a remote interrupt.
Single-5tep ... Writing a 1 with STRT low, the BCP
will single-step by executing the current instruction
and advancing the PC.
Fast Write ... When high, with LW low, selects fast
write mode for the buffered interface. When low
selects slow write mode.
Latched Read ... When high selects latched read
mode, when low selects buffered read mode.
Latched Write ... When high selects latched write
mode, when low selects buffered write mode.
STaRT . .. The remote system can start and stop
the BCP using this bit. On power-up/reset this bit is
low (BCP stopped). When set, the BCP begins executing
at the current Program Counter address.
When cleared, the BCP finishes executing the current
instruction, then halts to an idle mode.
In some applications, where there is no remote
system, or the remote system is not an intelligent
device, it may be desirable to have the BCP powerup/reset
running rather than stopped at address
OOOOH. This can be accomplished by asserting
REM-RD, REM-WR and RESET, with RAE de-asserted.
MS1,O Memory Select 1,0 ... These two bits determine
what the remote system is accessing in the BCP
system, according to the following table:
MS1
0
0
1
1
MSO
Selected Function
0 Data Memory
1 Instruction Memory
0 Program Counter (Low Byte)
1 Program Counter (High Byte)
The BCP must be idle for the remote system to
read/write Instruction memory or the Program
Counter.
All remote accesses are treated the same (independent
of where the access is directed using MSO
and MS1), as defined by the configuration bits LW,
LR, FW.
If the remote system and the BCP request data
memory access simultaneously, the BCP will win
first access. If the locks ([LOR], LOCK) are not set,
the remote system and BCP will alternate access
cycles thereafter.
On power-up/reset, MS1, 0 pOints to instruction
memory.
10.0 Transceiver
INTRODUCTION
The transceiver section operates as an on-chip, independent
peripheral, implementing all the necessary formatting
required to support the physical layer of the following serial
communications protocols:
• IBM 3270 (including 3299)
• IBM 5250
• NSC general purpose a-bit
The CPU and transceiver are tightly coupled through the
CPU register space, the transceiver appearing to the CPU
as a group of special function registers and three dedicated
interrupts. The transceiver consists of separate transmitter
and receiver logic sections, each capable of independent
operation, communicating with the CPU via an asynchronous
interface. This interface is software configurable for
both polled and interrupt-driven interaction, allowing the
system designer to optimize the BCP for the specific application.
The transceiver connects to the line through an external line
interface circuit which provides the required DC and AC
drive characteristics appropriate to the application. A block
diagram of such an interface is shown in Figure 35. An onchip
differential analog comparator, optimized for use in a
transformer coupled coax interface, is provided at the input
to the receiver. Alternatively, if an external comparator is
necessary, the input signal may be routed to the DATA-IN
pin.
The transceiver has several modes of operation. It can be
configured for Single line, half-duplex operation in which the
receiver is disabled while the transmitter is active Alternatively,
both receiver and transmitter can be active at the
same time for multi-channel (such as repeater) or loopback
operation. The transceiver has both internal and external
loopback capabilities, facilitating testing of both the software
and external hardware. At all times, both transmitter
and receiver operate according to the same protocol definition.
THE PROTOCOLS
In all protocols, data is transmitted serially in discrete messages
containing one or more frames, each representing a
single word of information. Biphase (Manchester II) encoding
is used, in which the data stream is divided into discrete
time intervals (bit-times) denoted by a level transition in the
center of the bit-time. For the IBM 3270, 3299 and NSC
general purpose a-bit protocols, a mid-bit transition from low
to high represents a biphase "1", and a mid-bit transition
from high to low represents a biphase "0". For the 5250
protocol, the definition of biphase logic levels is exactly reversed,
i.e. a biphase "1" is represented by a high to low
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