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~ National ~ Semiconductor - Al Kossow's Bitsavers

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7.0 CPU Registers (Continued)<br />

ICR INTERRUPT CONTROL REGISTER<br />

[Main R2; read/write]<br />

RIS1,O -<br />

Receiver Interrupt Select ... Defines the<br />

source of the Receiver Interrupt.<br />

RIS1,O Interrupt Source<br />

00 RFF + RE<br />

01 DAV + RE<br />

1 0 (unused)<br />

11 RA<br />

"+ .. indicates logical "or".<br />

7 6 5 4 3 2 1 0<br />

I RIS1 I RISO I rsv I IM4 11M3 11M2 I IM1 liMO I<br />

IM4-0 -Interrupt Mask ... Each bit, when set high,<br />

masks an interrupt. 1M3 functions as an interrupt<br />

mask only if BIRO is defined as an input. When<br />

BIRO is defined as an output, 1M3 controls the<br />

state of BIRO.<br />

IM4-0<br />

Interrupt<br />

00000 No Mask<br />

XXXX1 Receiver<br />

XXX1X Transmitter<br />

XX1XX Line Turn-Around<br />

X1XXX Bi-Directional<br />

1XXXX Timer<br />

ISP INTERNAL STACK POINTER<br />

[Main R30; read/write]<br />

ASP3-0- Address Stack Pointer ... Input/output port of<br />

the address stack pOinter. Further information:<br />

Chapter CPU.<br />

7 654 321 0<br />

76543210<br />

I TFE I RFF I LA I LTA I DEME I RAR I ACK I POLL I<br />

DEME - Data Error or Message End ... In 3270 & 3299<br />

modes, asserted when a byte parity error is detected.<br />

In 5250 modes, asserted when the [111]<br />

station address is decoded and [DAV] is asserted.<br />

Cleared by reading I RTR}. Undefined in<br />

8-bit modes and in the first frame of 3299<br />

modes.<br />

RAR - Received Auto-Response ... Set high when a<br />

3270 Auto-Response message is decoded and<br />

[RAR] is asserted. Cleared by reading I RTR I.<br />

Undefined in 5250 and 8-bit modes and in the<br />

first frame of 3299 modes.<br />

ACK - Poll/ ACKnowledge ... Set high when a 3270<br />

poll/ack command is decoded and [RAR] is asserted.<br />

Cleared by reading I RTR}. Undefined in<br />

5250 and 8-bit modes and in the first frame of<br />

3299 modes.<br />

POLL - POLL ... Set high when a 3270 poll command is<br />

decoded and [RAR] is asserted. Cleared by<br />

reading I RTR I. Undefined in 5250 and 8-bit<br />

modes and in the first frame of 3299 modes.<br />

RTR RECEIVE/TRANSMIT REGISTER<br />

[<strong>Al</strong>ternate R4; read/write]<br />

RTF7-0- Receive Transmit FIFO's ... Input/output port<br />

to the least significant eight bits of receive and<br />

transmit FIFO's. [OWPl, [TF10-8] and<br />

[RTF7 -0] are pushed onto the transmit FIFO on<br />

moves into IRTR}. [RF10-8] and [RTF7-0]<br />

are popped from receiver FIFO on moves out of<br />

I RTR I. Further information: Transceivers.<br />

7 6 5 4 321 0<br />

DSP3-0- Data Stack POinter ... Input/output port of the<br />

data stack pointer. Further information: Chapter<br />

CPU.<br />

NCF NETWORK COMMAND FLAG REGISTER<br />

[Main R1; read only]<br />

TFE - Transmit FIFO Empty ... Set high when the<br />

FIFO is empty. Cleared by writing to I RTR}.<br />

RFF - Receive FIFO Full ... Set high when the Receive<br />

FI FO contains 3 received words. Cleared<br />

by reading to I RTR}.<br />

LA - Line Active ... Indicates activity on the receiver<br />

input. Set high on any transition; cleared after<br />

detecting no input transitions for 16 TCLK periods.<br />

LTA - Line Turn Around ... Set high when end of<br />

message is received. Cleared by writing to<br />

I RTR I writing a "1" to this location, or by asserting<br />

[TRES].<br />

rsv. . state is undefined at all times<br />

TCR TRANSCEIVER COMMAND REGISTER<br />

[<strong>Al</strong>ternate R6; read/write]<br />

RLO - Receive Line Quiesce ... Selects number of<br />

line quiesce bits the receiver looks for.<br />

SEC<br />

SLR<br />

Number of<br />

RLQ<br />

Quiesces<br />

o 2<br />

1 3<br />

- Select Error Codes ... When high {ECR I is<br />

switched into {RTR I location.<br />

- Select Line Receiver ... Selects the receiver<br />

input source.<br />

SLR Source<br />

o TTL-IN<br />

1 On-chip analog<br />

line receiver<br />

2-135

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