~ National ~ Semiconductor - Al Kossow's Bitsavers

10.0 Transceiver (Continued)
actively processing an incoming signal, the receiver will be
disabled and flag the CPU that a "Receiver Disabled While
Active" error has occurred. (See Receiver Errors in this
Chapter.) On power-up/reset the transceiver defaults to this
half-duplex mode.
By asserting the Repeat Enable flag [RPEN], the receiver is
not disabled by the transmitter, allowing both transmitter
and receiver to be active at the same time. This feature
provides for the implementation of a repeater function or
loopback for test purposes.
The transmitter output can be connected to the receiver
input, implementing a local (on-chip) loopback, by asserting
[LOOP]. [RPEN] must also be asserted to enable both the
transmitter and receiver at the same time. With [LOOP] asserted,
the output TX-ACT is disabled, keeping the external
line driver in TRI-STATE. The internal flag [TA] is still enabled,
as are the serial data outputs.
Transmitter
The transmitter accepts parallel data from the CPU, formats
it according to the desired protocol and transmits it as a
serial biphase-encoded bit stream. A block diagram of the
transmitter logic is shown in Figure XR-6. Two biphase outputs,
DATA-OUT, DATA-DL Y, and the external line driver
enable, TX-ACT, provide the data and control signals for the
external line interface circuitry. The two biphase outputs are
valid only when TX-ACT is asserted (high) and provide the
necessary phase relationship to generate the "pre-emphasis"
waveform common to all of the transceiver protocols.
See Figure 14 for the timing relationships of these outputs
as well as the output of the line interface.
The capability is provided to invert DATA-OUT and DATA­
DL Y via the Transmitter Invert bit, [TIN], located in the
Transceiver Mode Register. DATA-DLY is always initialized
to the inverse state of [TIN]. In addition, the timing relationship
between TX-ACT and the two biphase outputs can be
modified with the Advance Transmitter Active control,
[ATA]. When [ATA] is cleared low (the power-up condition),
the transmitter generates exactly five line quiesce bits at the
start of each message, as shown in Figure 40. If [AT A] is
asserted high, the transmitter generates a sixth line quiesce
bit, adding one biphase bit time to the start sequence transmission.
The line driver enable, TX-ACT, is asserted halfway
through this bit time, allowing an additional half-bit (with no
pre-emphasis) to preceed the first line quiesce of the transmitted
waveform. This modified start sequence is depicted
in the dotted lines shown in Figure 40.
Data is loaded into the transmitter by writing to the Receivel
Transmit Register IRTRl, causing the first location of the
FIFO to be loaded with a 12-bit word (8-bits from IRTR}
and 4 bits from the Transceiver Command Register ITCR}.
The data byte to be transmitted is loaded into I RTR}, and
ITCR} contains additional information required by the protocol.
It is important to note that if ITCR} is to be changed,
it must be loaded before I RTR}. A multi-frame transmission
is accomplished by sequentially loading the FIFO with the
required data, the transmitter taking care of all necessary
frame formatting.
If the FIFO was previously empty, indicated by the Transmit
FIFO Empty flag [TFE] being asserted, the first word loaded
into the FIFO will asynchronously propagate to the last location
in approximately 40 ns, leaving the first two locations
empty. It is therefore possible to load up the FIFO with three
sequential instructions, at which time the Transmit FIFO Full
flag [TFF] will be asserted. If I RTR} is written while [TFF] is
high, the first location of the FIFO will be over-written and
data will be destroyed.
When the first word is loaded into the FIFO, the transmitter
starts up from idle, asserting TX-ACT and the Transmitter
Active flag [T A], and begins generating the start sequence.
After a delay of approximately 32 TCLK cycles (4 biphase
bit times), the word in the last location of the FIFO is loaded
into the encoder and prepared for transmission. If the FIFO
was full, [TFF] will be de-asserted when the encoder is
loaded, allowing an additional word to be loaded into the
FIFO.
When the last word in the FIFO has been loaded into the
encoder, [TFE] goes high, indicating that the FIFO is empty.
To ensure the continuation of a multi-frame message, more
data must then be loaded into the FIFO before the encoder
starts the transmission of the last bit of the current frame
(the frame parity bit for 3270, 3299, and 8-bit modes; the
last of the three mandatory fill bits for 5250). This maximum
load time from [TFE] can be calculated by subtracting two
from the number of bits in each frame of the respective
protocol, and multiplying that result by the bit rate. This
number represents the best case time to load-the worst
case value is dependent on CPU performance. Since the
CPU samples the transceiver flags and interrupts at instruction
boundaries, the CPU clock rate, wait states (from programmed
wait states, asserting the WAIT pin, or remote access
cycles), and the type of instruction currently being executed
can affect when the flag or interrupt is first presented
to the CPU.
If there is no further data to transmit (or if the load window is
missed), the ending sequence (if any) is generated and the
transmitter returns to idle, de-asserting TX-ACT and [T A].
Data should not be loaded into the FIFO after the transmitter
is committed to ending the message and before the [TA]
flag is deasserted. If this occurs, the load will be missed by
the transmitter control logiC and the word(s) will remain in
the FIFO. This condition exists when [TA] and [TFE] are
both low at the same time, and can be cleared by resetting
the transceiver (asserting [TRESl) or by loading more data
into the FIFO, in which case the first frame(s) transmitted
will contain the word(s) left in the FIFO from the previous
message.
Typical waveforms for transmitter operation are shown in
Figure 40.
2-172