~ National ~ Semiconductor - Al Kossow's Bitsavers

10.0 Transceiver (Continued)
dotted lines Indicate waveforms
with [ATA) set high
,....---"----,
I
DATA- DLY
I
I
I
I
._-----j
u
I
U----
I
LJI----
TRANSt.4ITTED
WAVEFORt.4
Receiver
IIne-quiesce
bit
The receiver accepts a serial biphase·encoded bit stream,
strips off the framing information, checks for errors and reo
formats the data for parallel transfer to the CPU. The block
diagram in Figure 41 depicts the data flow from the serial
input(s) to the FIFO's parallel outputs. Note that the FIFO
outputs are multiplexed with the Error Code Register {ECR)
outputs.
The receiver and transmitter share the same TCLK, though
in the receiver this clock is used only to establish the sam·
piing rate for the incoming biphase encoded data. All control
timing is derived from a clock signal extracted from this
data. Several status flags and interrupts are made available
to the CPU to handle the asynchronous nature of the incoming
data stream. See Figure 41 for the timing relationships
of these flags and interrupts relative to the incoming data.
The input source to the decoder can be either the on-chip
analog line receiver, the DATA·IN input or the output of the
transmitter (for on-chip loopback operation). Two bits, the
Select Line Receiver [SLR) and Loopback [LOOP), control
this selection. In addition, serial data can be inverted via the
Receiver Invert [RIN) control bit.
The receiver continually monitors the line, sampling at a frequency
equal to eight times the expected data rate. The
Line Active flag [LA) is asserted whenever an input transition
is detected and will remain asserted as long as another
input transition is detected within 16 TCLK cycles. If another
transition is not detected in this time frame, [LA) will
be de-asserted. This function is independent of the mode of
operation of the transceiver; [LA) will continue to respond to
input Signal transitions, even if the transmitter is activated
and the receiver disabled.
If the receiver is not disabled by the transmitter, the decoder
will adjust its internal timing to the incoming transitions, attempting
to synchronize to valid biphase·encoded data.
When synchronization occurs, the biphase clock will be extracted
and the serial NRZ (Non-Return to Zero) data will be
analyzed for a valid start sequence (see Figure 36 b). The
FIGURE 40. Transmitter Output
TLiF/9336-4S
minimum number of line quiesce bits required by the receiv·
er logic is selectable via the Receiver Line Quiesce [RLQ)
control bit. If this bit is set high (the power·up condition),
three line quiesce bits are required; if set low, only two are
needed. Once the start sequence has been recognized, the
receiver asserts the Receiver Active flag [RA) and enables
the error detection circuitry.
The NRZ serial bit stream is now clocked into a serial to
parallel shift register and analyzed according to the expected
data pattern as defined by the protocol. If no errors are
detected by the word parity bit, the parallel data (up to a
total of 11 bits, depending on the protocol) is passed to the
first location of the FIFO. It then propagates asynchronously
to the last location in approximately 40 ns, at which time the
Data Available flag [DAV) is asserted, indicating to the CPU
that valid data is available in the FIFO.
Of the possible 11 bits in the last location of the FIFO, 8 bits
(data byte) are mapped into {RTR) and the remaining bits
(if any) are mapped into the Transceiver Status Register
{TSR [0-2)). The CPU accesses the data byte by reading
{ RTR), and the 5250 address field or 3270 control bits by
reading {TSR). When reading the FIFO, it is important to
note that {TSR) must be read before {RTR), since reading
{RTR) advances the FIFO. Data in the FIFO will propagate
from one location to the next in approximately 10-15 ns,
therefore the CPU is easily able to unload the FIFO with a
set of consecutive instructions.
If the received bit stream is a multi-byte message, the receiver
will continue to process the data and load the FIFO.
After the third load (if the CPU has not accessed the FIFO),
the Receive FIFO Full flag [RFF) will be asserted. If there
are more than 3 frames in the incoming message, the CPU
has approximately one frame time (sync bit to start of parity
bit) to start unloading the FI FO. Failure to do so will result in
an overflow error condition and a resulting loss of data (see
Receiver Errors).
If there are no errors detected, the receiver will continue to
process the incorning frames until the end of message is
detected. The receiver will then return to an inactive state,
2-173