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6.0 Connection Diagrams Dual-In-Llne Package z ~ CD U"I CD MR cr lID WI! ALE ADO ADI ADZ AD3 Leadless Chip Carrier GND 14 ..... _--_ ... TLlC/5593-23 Top View 16 XOUT 15 XIN Order Number NSC858D or N See NS Package D28C or N28B Plastic Chip Carrier NC ALE ADO ADI AD2 HC AD3 AD4 ADS HC 6 5 4 3 2 1 44 43 42 41 40 39 38 37 10 36 11 35 12 NSC858E 34 13 33 14 32 15 31 16 30 NC iiTR Ri'S DeD iffi HC RxD Rx C/BRGOUT TxD TxC/BRGOUT HC ALE ADO ADI ADZ HC AD3 AD4 ADS NC 6 5 4 3 2 1 44 43 42 41 40 39 38 9 37 10 36 11 35 12 NSC858V 34 13 33 14 32 15 31 16 30 NC iiTR Ri'S DCD iffi NC RxD R xC/BRGDUT TxD Tx C/BRGOUT NC 17 29 18 19 20 21 22 23 24 25 26 27 28 HC NC 17 29 18 19 20 21 22 23 24 25 26 27 28 NC Top View TL/C/5593-24 Top View TL/C/5593-25 Order Number NSC858E See NS Package Number E44A Order Number NSC858V See NS Package Number V44A 7.0 Pin Descriptions 7.1 INPUT SIGNALS Master Reset (MR): active high, Pin 1. This Schmitt trigger input has a 0.5V typical hysteresis. When high, the following registers are cleared: receiver mode, transmitter mode, global mode, R·T status (except for TxBE which is set to one), R·T status mask, modem mask, command (which disables receiver "Rx" and the transmitter "Tx"), power down, and receiver holding. In the modem status register, IlCTS, 1l0CO, 1l0SR, BRK and IlBRK are cleared. Chip Enable (CE): active low, Pin 2. Chip enable must be low during a valid read or write pulse in order to select the device. Chip enable is not latched. Read (RD): active low, Pin 3. While the chip is enabled the CPU latches data from the selected register on the rising edge of RO. Write (WR): active low, Pin 4. While the chip is enabled it latches data from the CPU on the riSing edge of WR. Address Latch Enable (ALE): negative edge sensitive, Pin 5. The negative edge (high to low) of ALE latches the address for the register select during a read or write operation. 4-103
= r---------------------------------------------------------------. It) = (,) CJ) z 7.0 Pin Descriptions (Continued) Power Down (PO): active low, Pin 1? When active it disables all internal clocks, shuts off the oscillator, clears RxE, TxE, and break control bits in the command register. <strong>Al</strong>l other registers retain their data. Unlike software power down, PO also disables the internal ALE, CE, RD, WR, address and data paths for minimum power consumption. Registers cannot be accessed in hardware power down; they may be in software power down. Receiver Data (RxD): Pin 21. This accepts serial data input from the communications link (peripheral device, modem, or data set). Serial data is received least significant bit (LSB) first. "Mark" is high (1), "space" is low (0). Data Carrier Detect (DCD): active low, Pin 23. Can be used as a modem or general purpose input. When this modem input is low it indicates that the data carrier has been detected by the modem or data set. The DCD signal is a modem control function input whose complement value can be tested by the CPU by reading bit 5 (DCD) of the modem status register. Bit 1 (,lOCO) of the modem status register indicated whether the DCD input has changed state since the previous reading of the modem status register. DCD can also be programmed to become an auto enable for the receiver. NOTE: Whenever the DeD bit of the modem status register changes state, an interrupt is generated if the
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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Page 464 and 465: 3. The Rx FIFO will hold 16 bytes r
Page 466 and 467: NS16550A E-J r-o ..... IRQ4 ICU CPU
Page 468 and 469: TITLE 550APP.ASM - NS16550A INITIAL
Page 470 and 471: 3.0 Board to Board Communications w
Page 472 and 473: DIAPPS.ASM Flow Chart l> z • ~ CO
Page 474 and 475: » z I "" CD RDAI: DISABLE IRTS, SE
Page 476 and 477: COMPARE: SET UP COMPARE BUffER POIN
Page 478 and 479: .set iCu imsk,lO *aO • set icu -c
Page 480 and 481: holdloop: nop # br hold loop # # #*
Page 482 and 483: # msint: save [rO,rl,r2,r3] # movd
Page 484 and 485: #3/30/B7••••• D2APPS.ASM
Page 486 and 487: # #*************************** 1655
Page 488 and 489: -----------------------------------
Page 490 and 491: A Comparison of the I NS8250, NS 16
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Page 494 and 495: cessed (see Figure 4), The output o
Page 496 and 497: AC Electrical Characteristics T A =
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Page 500 and 501: 1.0 Absolute Maximum Ratings 2.0 Op
Page 502 and 503: 4.0 AC Electrical Characteristics (
Page 504 and 505: 5.0 Timing Waveforms (Continued) ii
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Page 510 and 511: 8.0 Block Diagram CPU INTERFACE INT
Page 512 and 513: 9.0 Registers (Continued) Bit three
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Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
Page 521 and 522: Absolute Maximum Ratings (Notes 1 &
Page 523 and 524: fj ::z:: ~ :::IE :::IE ~ ,---------
Page 525 and 526: Applications Information (Continued
Page 527 and 528: Absolute Maximum Ratings (Notes 1 &
Page 529 and 530: Description of Pin Functions Pin No
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Page 535 and 536: Electrical Characteristics Unless o
Page 537 and 538: C'I 5 Pin Descriptions (Continued)
Page 539 and 540: IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
Page 541 and 542: Functional Description (Continued)
Page 543 and 544: Functional Description (Continued)
Page 545 and 546: Absolute Maximum Ratings* If Milita
Page 547 and 548: Electrical Characteristics unless o
Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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Page 557 and 558: ..... U) z • U) r----------------
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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