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---------------------------------------------------------------------~ C ~National ~ Semiconductor DS78LS 120/DS88LS 120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) General Description The DS78LS120 and DS88LS120 are high performance, dual differential, TTL compatible line receivers for both balanced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. The line receiver will discriminate a ± 200 mV input signal over a common-mode range of ± 10V and a ± 300 mV signal over a range of ± 15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes an optional 1800 terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78LS120 is specified over a - 55'C to + 125'C temperature range and the DS88LS120 from O'C to + 70'C. Input specifications meet or exceed those of the popular DS7820/DS8820 line receiver. Features • Meets EIA standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114 • Input voltage range of ± 15V (differential or commonmode) • Separate strobe input for each receiver • 5k typical input impedance • Optional 1800 termination resistor • 50 mV input hysteresis • 200 mV input threshold • Separate fail-safe mode en ...... Q) In ... ~ ~ ~ Q) In ... ~ Q Connection Diagram Dual-ln·Llne Package FAIL·SAFE TERMI· RESPONSE OFFSET -INPUT NATION +INPUT STROBE TIME OUTPUT 15 14 13 12 11 10 4 FAIL·SAFE -INPUT TERMI· +INPUT STROBE RESPONSE OUTPUT OFFSET NATION TIME Top View Order Number DS78LS120J, DS88LS120J or DS88LS120N See NS Package Number J16A or N16A Tl/FI7499-1 6-23
~National ~ Semiconductor DS8921/DS8921 A Differential Line Driver and Receiver Pair General Description The DS8921, DS8921 A are Differential Line Driver and Receiver pairs designed specifically for applications meeting the ST506, ST412 and ESDI Disk Drive Standards. In addition, these devices meet the requirements of the EIA Standard RS-422. The DS8921A receiver offers an input sensitivity of 200 mV over a ± 7V common mode operating range. Hysteresis is incorporated (typically 70 mV) to improve noise margin for slowly changing input waveforms. An input fail-safe circuit is provided such that if the receiver inputs are open the output assumes the logical one state. The DS8921A driver is designed to provide unipolar differential drive to twisted pair or parallel wire transmission lines. Complementary outputs are logically ANDed and provide an output skew of 0.5 ns (typ.) with propagation delays of 12 ns. Power up/down circuitry is featured which will TRI-STATE® the outputs and prevent erroneous glitches on the transmission lines during system power up or power down operation. The DS8921A is designed to be compatible with TTL and CMOS. Features • 12 ns typical propagation delay • Output skew - 0.5 ns typical • Meet the requirements of EIA Standard RS-422 • Complementary Driver Outputs • High differential or common-mode input voltage ranges of ±7V • ± 0.2V receiver sensitivity over the input voltage range • Receiver input fail-safe circuitry • Receiver input hysteresis-70 mV typical • Glitch free power up/down Connection Diagram VCC...!.~~~RI+ 2 f---1 7 RO - I ..... r- RI- 01 ~IL ~~_-I_6_ 00+ GNO - /'{.L-___ 1-5;... 00- TL/F/8512-1 Order Number DS8921M, DS8921N, DS8921AM, DS8921AN, DS8921J or DS8921AJ See NS Package Number J08A, M08A or N08E Truth Table Receiver Driver Input VOUT Input VOUT o o o o For complete specifications see the Interface Databook. 6-24
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Page 547 and 548: Electrical Characteristics unless o
Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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Page 570 and 571: Section 6 Transmission Line Drivers
Page 572 and 573: ~National ~ Semiconductor Transmiss
Page 574 and 575: ~National ~ Semiconductor OS 1488 Q
Page 576 and 577: J?'A National ~ Semiconductor OS 14
Page 578 and 579: ~National ~ Semiconductor DS26C31 C
Page 580 and 581: ~National ~ Semiconductor DS26C32C
Page 582 and 583: ~National ~ Semiconductor DS34C86 Q
Page 584 and 585: ~National ~ Semiconductor PRELIMINA
Page 586 and 587: ~National ~ Semiconductor DS1692/DS
Page 588 and 589: ~National ~ Semiconductor DS75150 D
Page 590 and 591: ~National ~ Semiconductor DS75176A/
Page 594 and 595: ~National ~ Semiconductor DS8922/22
Page 596 and 597: ~National ~ Semiconductor DS96172/~
Page 598 and 599: ~National ~ Semiconductor DS961771
Page 600 and 601: ~National ~ Semiconductor DS9637 AI
Page 602 and 603: • I .----------------------------
Page 604 and 605: Section 7 Physical Dimensions
Page 606 and 607: ~National ~ Semiconductor All dimen
Page 608 and 609: NS Package N16A N16A(REV E) 0.092 X
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Page 612 and 613: 0.11M-0.118 (2.642-2.9971 .. ••
Page 614 and 615: NOTES
Page 616 and 617: ~National ~ Semiconductor Bookshelf
Page 618 and 619: RELIABILITY HANDBOOK-1986 Reliabili
Page 620 and 621: NATIONAL SEMICONDUCTOR CORPORATION
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