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10.0 Transceiver (Continued) TABLE XXVI. Protocol Mode Definition PS2-0 Protocol Mode Comments 000 001 010 01 1 100 101 110 1 1 1 3270 Standard IBM 3270 protocol. 3299 Multiplexer Receiver expects first frame to be address frame. Transmitter uses standard 3270, no address frame. 3299 Controller Transmitter generates address frame as first frame. Receiver expects standard 3270, no address frame. 3299 Repeater Both transmitter and receiver operate with first frame as address frame. 5250 Non-promiscuous mode. IDA V] asserted only when first frame address matches {ATRI. 5250 Promiscuous IDA V] asserted on all valid received data without regard to address field. a-Bit General-purpose a-bit protocol with first frame address. Non-promiscuous mode. IDA V] asserted only when first frame address matches {NAR I. a-Bit Promiscuous IDA V] asserted on all valid received frames. CPU regist ... DATA-IN +ALG-IN -ALG-IN ,..------+1X- ACT r-~ ........ ...,I-~--+DATA- DLY .....___....I",.~~__ ~DATA-OUT loopback TL/F/9336-44 KEY TO REGISTERS RTR TSR TCR TMR Receive/Transmit Register ATR Auxiliary Transceiver Register Transceiver Status Register NCF Network Command Register Transceiver Command Register FBR Fill-Bit Register Transceiver Mode Register OCR Device Control Register FIGURE 39. Block Diagram of Transce ver, Showing CPU Interface 2-171
10.0 Transceiver (Continued) actively processing an incoming signal, the receiver will be disabled and flag the CPU that a "Receiver Disabled While Active" error has occurred. (See Receiver Errors in this Chapter.) On power-up/reset the transceiver defaults to this half-duplex mode. By asserting the Repeat Enable flag [RPEN], the receiver is not disabled by the transmitter, allowing both transmitter and receiver to be active at the same time. This feature provides for the implementation of a repeater function or loopback for test purposes. The transmitter output can be connected to the receiver input, implementing a local (on-chip) loopback, by asserting [LOOP]. [RPEN] must also be asserted to enable both the transmitter and receiver at the same time. With [LOOP] asserted, the output TX-ACT is disabled, keeping the external line driver in TRI-STATE. The internal flag [TA] is still enabled, as are the serial data outputs. Transmitter The transmitter accepts parallel data from the CPU, formats it according to the desired protocol and transmits it as a serial biphase-encoded bit stream. A block diagram of the transmitter logic is shown in Figure XR-6. Two biphase outputs, DATA-OUT, DATA-DL Y, and the external line driver enable, TX-ACT, provide the data and control signals for the external line interface circuitry. The two biphase outputs are valid only when TX-ACT is asserted (high) and provide the necessary phase relationship to generate the "pre-emphasis" waveform common to all of the transceiver protocols. See Figure 14 for the timing relationships of these outputs as well as the output of the line interface. The capability is provided to invert DATA-OUT and DATA DL Y via the Transmitter Invert bit, [TIN], located in the Transceiver Mode Register. DATA-DLY is always initialized to the inverse state of [TIN]. In addition, the timing relationship between TX-ACT and the two biphase outputs can be modified with the Advance Transmitter Active control, [ATA]. When [ATA] is cleared low (the power-up condition), the transmitter generates exactly five line quiesce bits at the start of each message, as shown in Figure 40. If [AT A] is asserted high, the transmitter generates a sixth line quiesce bit, adding one biphase bit time to the start sequence transmission. The line driver enable, TX-ACT, is asserted halfway through this bit time, allowing an additional half-bit (with no pre-emphasis) to preceed the first line quiesce of the transmitted waveform. This modified start sequence is depicted in the dotted lines shown in Figure 40. Data is loaded into the transmitter by writing to the Receivel Transmit Register IRTRl, causing the first location of the FIFO to be loaded with a 12-bit word (8-bits from IRTR} and 4 bits from the Transceiver Command Register ITCR}. The data byte to be transmitted is loaded into I RTR}, and ITCR} contains additional information required by the protocol. It is important to note that if ITCR} is to be changed, it must be loaded before I RTR}. A multi-frame transmission is accomplished by sequentially loading the FIFO with the required data, the transmitter taking care of all necessary frame formatting. If the FIFO was previously empty, indicated by the Transmit FIFO Empty flag [TFE] being asserted, the first word loaded into the FIFO will asynchronously propagate to the last location in approximately 40 ns, leaving the first two locations empty. It is therefore possible to load up the FIFO with three sequential instructions, at which time the Transmit FIFO Full flag [TFF] will be asserted. If I RTR} is written while [TFF] is high, the first location of the FIFO will be over-written and data will be destroyed. When the first word is loaded into the FIFO, the transmitter starts up from idle, asserting TX-ACT and the Transmitter Active flag [T A], and begins generating the start sequence. After a delay of approximately 32 TCLK cycles (4 biphase bit times), the word in the last location of the FIFO is loaded into the encoder and prepared for transmission. If the FIFO was full, [TFF] will be de-asserted when the encoder is loaded, allowing an additional word to be loaded into the FIFO. When the last word in the FIFO has been loaded into the encoder, [TFE] goes high, indicating that the FIFO is empty. To ensure the continuation of a multi-frame message, more data must then be loaded into the FIFO before the encoder starts the transmission of the last bit of the current frame (the frame parity bit for 3270, 3299, and 8-bit modes; the last of the three mandatory fill bits for 5250). This maximum load time from [TFE] can be calculated by subtracting two from the number of bits in each frame of the respective protocol, and multiplying that result by the bit rate. This number represents the best case time to load-the worst case value is dependent on CPU performance. Since the CPU samples the transceiver flags and interrupts at instruction boundaries, the CPU clock rate, wait states (from programmed wait states, asserting the WAIT pin, or remote access cycles), and the type of instruction currently being executed can affect when the flag or interrupt is first presented to the CPU. If there is no further data to transmit (or if the load window is missed), the ending sequence (if any) is generated and the transmitter returns to idle, de-asserting TX-ACT and [T A]. Data should not be loaded into the FIFO after the transmitter is committed to ending the message and before the [TA] flag is deasserted. If this occurs, the load will be missed by the transmitter control logiC and the word(s) will remain in the FIFO. This condition exists when [TA] and [TFE] are both low at the same time, and can be cleared by resetting the transceiver (asserting [TRESl) or by loading more data into the FIFO, in which case the first frame(s) transmitted will contain the word(s) left in the FIFO from the previous message. Typical waveforms for transmitter operation are shown in Figure 40. 2-172
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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5.0 Instruction Set Overview (Conti
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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4.0 Timing Waveforms (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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TABLE III. Remote Digital Loopback
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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