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~ ~ HASM state TCU state eLK-OUT REM-RD RS ... Tl RS ... Tx RSA TWd RS ... T2 RS B La. I I ' XACK READ ALE T, RSC TWr RSO TWr RSO TWd r- DAT ... MEMORY ACCESS:1 RS E TWr BCP BUS R5E TWr LOCAL DATA xmzIIOIIOIIlX"------R-EM-OTE-DA-TA----->eZZ>E:3( LOCAL DATA 'Qll I LOCAL ADDRESS 'mzl)( REMOTE ... DDRESS X LOCAL ADDRESS 'Qll REMOTE BUS ADDRESS !llX REMOTE ADDRESS xIIIIIIIIIIlllO I DATA mzmoozzozZZZZZZZlllZ/ZZlllllTl/Xu REMOTE DATA X///I/11lj//IIljlllj/ I I L- LOCAL MEMORY READ ~ '----------- REMOTE READ ------------1 L LOCAL MEMORY READ ~ RS E TWr RS E TWr RSr TWr RS ... TWr RS ... Tx RS ... TWd RS ... T2 RS ... Tl TUF/9336-27 CD b ::D CD 3 o -CD :::J -CD ::::. I» n CD I» :::J a. » .." 0" ;:; D1 -0- :::J 1 CD 3 '§ :::> C!: :::> c: ~ Register Configuration: -One Wait-State Programmed for Data-Memory -Zero Wait-States Programmed for Instruction-Memory -{RICl Contents: XXXOX100 -[LOR] = 0 Other BCP Control Signals: RAE =0 CMD =0 REM-WR =1 LOCK =1 FIGURE 26_ Buffered Read of Data Memory by Remote Processor Vtt£8da
8.0 Remote Interface and Arbitration System (Continued) The last possible Memory Selection is Instruction Memory, state machine (RASM) loops in state RSA. If [LOR) is set [MS1-0) = 01. The two possible next states for an IMEM high, RASM will loop in RSA indefinitely. If the BCP CPU access depend on if RASM is expecting the low byte or high needs to access Data Memory at this time (and LOCK is byte. Instruction words are accessed low byte then high high), it can still do so. A local access is requested by the byte and RASM powers up expecting the low Instruction Timing Control Unit asserting the Local Bus Request byte. The internal flag that keeps track of the next expected (LCL-BREQ) signal. A local bus grant will be given by RASM Instruction byte is called the High Instruction Byte flag (HI B). if the buses are not being used (as is the case in RSA). If HIB is low, the next state is RS05 and the low instruction XACK is taken low as soon as RAE*REM-RD is true, rebyte is MUXed to the AD bus. If HIB is "1 ", the high instruc- gardless of an ongoing local access. RASM will move into tion byte is MUXed to AD and RS06 is entered if HIB = 1. RSs on the next clock after RAE*REM-RD is asserted and An IMEM access, like a DMEM access, is subject to wait there is no local bus request. No further local bus requests states and these states will be looped on until all pro- will be granted until the BCP enters the Termination Phase. grammed instruction memory wait states have been insert- If the BCP CPU initiates a Data Memory Access after RSA, ed. the Timing Control Unit will be waited and the BCP CPU will <strong>Al</strong>l the RSo states eventually move to their corresponding remain in state T Wr until the Remote Access reaches the RSE states on the clock after the wait state conditions, if Termination Phase. any, are met. The RSE states are looped upon until On the next clock, RASM enters RSc and LCL is asserted RAE*REM-RD is deasserted and WAIT is high. LCL is still along with XACK. The wait state counters, ilW and iow, are high in this state and A remains in TRI-STATE. AD will also loaded in this state lrom [lW1-0) and [DW2-0), respectivestay in TRI-STATE il the access was to DMEM. XACK is Iy, in (OCR). The A bus (and AD il the access is to Data taken back high to indicate that data is now valid on the Memory) now goes into TRI-STATE and the Access Phase read. II XACK is connected to a Remote Processor wait pin, begins. it is no longer waited and can now terminate its read cycle. The state machine can move into one 01 several states de- This state begins the Termination Phase. The action speci- pending CMD and [MS1-0) on the next clock. XACK and lied in the conditional box is only executed while RAE*REM- LCL are still asserted in all the possible next states. II CMD RD is asserted-a clock edge is not necessary. is high, the access is to (RIC) and the next state will be On the CPU-CLK after RAE*REM-RD is deasserted, RASM RS01. Since the delault state 01 AD is (RIC), it will not enters RSF, where LCL is high and the TRI-STATE condi- transition in this state. The live other next states all have tion in RSE remains in effect. The next clock brings the state CMD low and depend on the Memory Select bits. machine back to RSA state where it will loop until another II [MS1-0) is 10 or 11 the state machine will enter either Remote Access is initiated. If the access was to IMEM, then RS02 or RS03 and the low or high bytes of the Program the last action 01 the remote access belore returning to RSA Counter, respectively, will be read. is to switch HIB and increment the PC il the high byte was [MS1-0) = 00 designates a Data Memory access and read. moves RASM into RS04' READ will be asserted in this state The example in Figure 26 shows the BCP executing the first and A and AD continue to be at TRI-STATE. This allows the 01 two consecutive Data Memory reads when REM-RD goes Remote Processor to drive the Data Memory address for low. In response, XACK goes low waiting the remote proc- the read. Since DMEM is subject to wait states, RS04 is essor. At the end of the first instruction, although the BCP looped upon until all the wait states have been inserted. begins its second read by taking ALE high, the RASM now The last possible Memory Selection is Instruction Memory, takes control of the bus and takes LCL high at the end of [MS1-0) = 01. The two possible next states lor the IMEM T1· A one T-state delay is built into this transfer to ensure access depend on if RASM is expecting the low byte or high that READ has been deasserted belore the data bus is byte. Instruction words are accessed low byte then high switched. The Timing Control Unit is now waited, inserting byte and RASM powers up expecting the low Instruction remote access wait states, T Wr, as RASM takes over. byte. The internal Ilag that keeps track of the next expected The remote address is permitted one T-state to settle on the Instruction byte is called the High Instruction Byte flag (HIB). BCP address bus before READ goes low, XACK then re- If HIB is low, the next state is RS05 and the low instruction turns high one T-state plus the programmed Data Memory byte is MUXed to the AD bus. If HIB is "1" , the high instrucwait state, TWd later, having satislied the memory access tion byte is MUXed to AD and RS06 is entered if HIB = 1. time. The Remote Processor will respond by removing An IMEM access, like a DMEM access, is subject to wait REM-RD to which the BCP in turn responds by removing states and these states will be looped on until all pro- READ. Following the removal 01 READ, the BCP waits till grammed instruction memory wait states have been insertthe end 01 the next T-state before taking LCL low, again ed. ensuring that the read cycle has concluded before the bus is switched. Control is then returned to the Timing Control Unit and the local memory read continues. Latched Read This mode differs from the Buffered Read mode in the way the access is terminated. A latched Read cycle ends after the data being read is valid and the termination doesn't wait for the trailing edge of REM-RD. Therefore the Arbitration and Access Phases of the Latched Read mode are the same as for the Buffered Read mode. The complete flow chart for the Latched Read mode is shown in Figure 27. Until a Remote Read is initiated (RAE*REM-RD true), the 2-154 <strong>Al</strong>l the RSo states move to their corresponding RSE states on the CPU-CLK after wait state conditions are met and WAIT is high. LCL is asserted in all RSE states and A remains in TRI-STATE (and AD if the access is to Data Memory). XACK returns high in this state, indicating that data is valid so that it can be externally latched. The action specific to each RSo state remains in effect during the first half of the RSE cycle (Le. READ is asserted in the first half of RSE4). This hall T-state of hold time is provided to guarantee data is latched when XACK goes high. This state begins the Termination Phase.
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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Page 348 and 349: Decoding Bit Fields with the JRMK I
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Page 354 and 355: "Interrupts"-A Powerful Tool of the
Page 356 and 357: TABLE II. (lCR) Interrupt Mask Bits
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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