~ National ~ Semiconductor - Al Kossow's Bitsavers

13.0 Bus Arbitration and Timing (Continued)
SLAVE MODE TIMING
When CS is low, the NIC becomes a bus slave. The CPU
can then read or write any internal registers. All register
access is byte wide. The timing for register access is shown
below. The host CPU accesses internal registers with four
address lines, RAO-RA3, SRD and SWR strobes.
ADSO is used to latch the address when interfacing to a
multiplexed, address data bus. Since the NIC may be a local
bus master when the host CPU attempts to read or write to
the controller, an ACK line is used to hold off the CPU until
the NIC leaves master mode. Some number of BSCK cycles
is also required to allow the NIC to synchronize to the read
or write cycle.
C
"'til
co
W
fD
o
....
......
Z
~
N
"'"
fD
o
....
---------c~~=~
~ ____________
~r_
~ _ ____"r_
TLIF/9345-34
~_~r_
~ ____________ ~r_
TL/F/9345-35
1-85