~ National ~ Semiconductor - Al Kossow's Bitsavers

7.0 CPU Registers (Continued)
BIT INDEX
An alphabetical listing of all status/control bits in the CPU-addressable special function registers, with a brief summary of
function. Detailed definitions are provided in the Bit Definition Table. (Continued)
Bit Name Location Function
TFE Transmit FIFO Empty NCF
TFF Transmit FIFO Full TSR
TIN Transmitter INvert TMR
TlD Timer LoaD ACR
TM7-0 TiMer TRl
TM15-B TiMer TRH
TMC TiMer Clock select ACR
TO Time Out flag CCR
TRES Transceiver RESet TMR
TST Timer StarT ACR
V oVerflow CCR
Z Zero CCR
[7] Transmitter Status
[7] Transmitter Status
[3] Transmitter Control
[6] Timer
[7-0] Timer
[7-0] Timer
[5]
[7]
[7]
[7]
[2]
[0]
Timer
Timer
Transceiver Control
Timer
Arithmetic Flag
Arithmetic Flag
REGISTER OVERVIEW
A list of all CPU-addressable special function registers, in
alphabetical order.
The Remote Interface Configuration register (RIC), which is
addressable only by the remote system, is not included. See
Section B.O for details of the function of this register.
Each register is listed together with its address, the type of
access available, and a functional description of each bit.
Further details on each bit can be found in the "Bit Definition
Table".
ACR AUXILLIARY CONTROL REGISTER
[Main R3; read/write]
TST - Timer StarT ... When high, the timer is enabled
and will count down from it's current value.
TlD
TMC
7
When low, timer is disabled. Timer is stopped by
writing a 0 to [TST].
I TST I TlD I TMC I BIC I rsv I COD I lOR I GIE I
BIC
COD
- Timer LoaD ... When high, generates timer load
pulse. Cleared when load complete.
- Timer Clock Select ... Selects timer clock frequency.
Should not be written when [TST] is
high. Can be written at same time as [TST] and
[TlD].
TCS
Timer Clock
0 (CPU-ClK)/16
1 (CPU-CLK)/2
6 5 4 3 2 1 0
- Bi-directional Interrupt Control ... Controls direction
of BIRQ.
BIC
o
BIRQ
Input
1 Output
- Clock Out Disable ... When high, ClK-OUT output
is at TRI-ST ATE.
lOR - Lock Out Remote ... When high, a remote system
is prevented from accessing the BCP.
GIE - Global Interrupt Enable ... When low, disables
all maskable interrupts. When high, works with
[lM4-0] to enable maskable interrupts.
ATR AUXILLIARY TRANSCEIVER REGISTER
[Alternate R2; read/write]
A T7 -0 - Auxiliary Transceiver ... In 5250 protocol
modes, bits 2-0 define the receive station address,
and bits 7-3 control the amount of time
TX-ACT stays asserted after the last fill bit.
In B-bit protocol modes, bits 7-0 define the receive
station address.
For further information, see Transceiver Section.
7
ATR7-3 TX-ACT Hold Time (,...s)
00000 0
00001 0.5
00010 1.0
0001 1 1.5
-J..
-J..
1 1 1 1 1 15.5
6 5 4 3 2 1 0
I AT7 I AT6 I AT5 I AT4 I AT3 I AT2 I ATl I ATO I
CCR CONDITION CODE REGISTER
[Main RO; bits 0-3, 5-7 read/write, bit 4 read only]
TO - Time Out Flag ... Set high when timer counts to
zero. Cleared by writing a 1 or stopping the timer
(by writing a 0 to [TSTl).
RR - Remote Read ... Set on the trailing edge of a
REM-RD pulse, if RAE is asserted and (RIC) is
pOinting to Data Memory. Cleared by writing a 1
to this location.
RW - Remote Write ... Set on the trailing edge of a
REM-WR pulse, if RAE is asserted and (RIC) is
pOinting to Data Memory. Cleared by writing a 1
to this location.
rsv ... state is undefined at all times.
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