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6.0 Pin Descriptions (Continued) OLAB A2 A1 Ao Register 0 0 0 0 Receiver Buffer (read), Transmitter Holding Register (write) 0 0 0 1 Interrupt Enable X 0 1 0 Interrupt Identification (read only) X 0 1 1 Line Control X 1 0 0 MODEM Control X 1 0 1 Line Status X 1 1 0 MODEM Status 1 0 0 0 Divisor Latch (least significant byte) 1 0 0 1 Divisor Latch (most significant byte) Register Addresses Master Reset (MR), Pin 35: When this input is high, it clears all the registers (except the Receiver Buffer, Transmitter Holding, and Divisor Latches), and the control logic of the UART. The states of various output signals (SOUT, INTR, OUT 1, OUT 2, RTS, DTR) are affected by an active MR input. (Refer to Table I.). Receiver Clock (RCLK), Pin 9: This input is the 16 x baud rate clock for the receiver section of the chip. Serial Input (SIN), Pin 10: Serial data input from the communications link (peripheral device, MODEM, or data set). Clear to Send (CTS), Pin 36: When low, this indicates that the MODEM or data set is ready to exchange data. The CTS signal is a MODEM status input whose conditions can be tested by the CPU reading bit 4 (CTS) of the MODEM Status Register. Bit 4 is the complement of the CfS signal. Bit 0 (DCTS) of the MODEM Status Register indicates whether the CTS input has changed state since the previous reading of the MODEM Status Register. CTS has no effect on the Transmitter. Nota: Whenever the CTS bit of the MODEM Status Register changes state, an interrupt is generated H the MODEM Status Interrupt is enabled. Data Set Ready (OSR), Pin 37: When low, this indicates that the MODEM or data set is ready to establish the communications link with the UART. The DSR signal is a MODEM status input whose condition can be tested by the CPU reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has changed state since the previous reading of the MODEM Status Register. Note: Whenever the DSR bH of the MODEM Status Register changes slate, an interrupt is generated if the MODEM Status Interrupt is enabled. Data Carrier Detect (DCO), Pin 38: When low, indicates that the data carrier has been detected by the MODEM or data set. The DCD signal is a MODEM status input whose condition can be tested by the CPU reading bit 7 (DCD) of the MODEM Status Register. Bit 7 is the complement of the l5CD signal. Bit 3 (DDCD) of the MODEM Status Register indicates whether the i5C5 input has changed state since the previous reading of the MODEM Status Register. DCD has no effect on the receiver. Nota: Whenever the DCD bit of the MODEM Slatus Register changes state, an interrupt is generated H the MODEM Slatus Interrupt is enabled. Ring Indicator (Ai), Pin 39: When low, this indicates that a telephone ringing signal has been received by the MODEM or data set. The Ai signal is a MODEM status input whose condition can be tested by the CPU reading bit 6 (RI) of the MODEM Status Register. Bit 6 is the complement of the Ai signal. Bit 2 (TERI) of the MODEM Status Register indicates whether the Ai input signal has changed from a low to a high state since the previous reading of the MODEM Status Register. Note: Whenever the RI bit of the MODEM Status Register changes from a high to a low slate, an interrupt Is generated H the MODEM Status Interrupt is enabled. Vee, Pin 40: + 5V supply. Vss, Pin 20: Ground (OV) reference. 6.2 OUTPUT SIGNALS Data Terminal Ready (OTR), Pin 33: When low, this informs the MODEM or data set that the UART is ready to establish a communications link. The DTR output signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Request to Send (RTS), Pin 32: When low, this informs the MODEM or data set that the UART is ready to exchange data. The RTS output signal can be set to an active low by programming bit 1 (RTS) of the MODEM Control Register. A Master Reset operation sets this signal to its inactive (high) state. Output 1 (OUT 1), Pin 34: This user-designated output can be set to an active low by programming bit 2 (OUT 1) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. In the XMOS parts this will achieve TTL levels. Output 2 (OUT 2), Pin 31: This user-designated output can be set to an active low by programming bit 3 (OUT 2) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. In the XMOS parts this will achieve TTL levels. Chip Select Out (CSOUT), Pin 24: When high, it indicates that the chip has been selected by active, CSO, CS1, and CS2 inputs. No data transfer can be initiated until the CSOUT signal is a logic 1. CSOUT goes low when the UART is deselected. Driver Disable (OOIS), Pin 23: This goes low whenever the CPU is reading data from the UART. It can disable or control the direction of a data bus transceiver between the CPU and. the UART (see Typical Interface for a High Capacity Data Bus). Baud Out ('''B'''A''U'''O'''O''U""'n, Pin 15: This is the 16 x clock signal from the transmitter section of the UART. The clock rate is equal to the main reference oscillator frequency divided by the specified divisor in the Baud Generator Divisor Latches. The BAUDOUT may also be used for the receiver section by tying this output to the RCLK input of the chip. 4-11
6.0 Pin Descriptions (Continued) Interrupt (INTR), Pin 30: This goes high whenever anyone of the following interrupt types has an active high condition and is enabled via the IER: Receiver Line Status; Received Data Available; Transmitter Holding Register Empty; and MODEM Status. The INTR signal is reset low upon the ap- propriate interrupt service or a Master Reset operation. 7.0 Connection Diagrams Dual-In-Line Package DD~r-~CC 6.3 INPUT/OUTPUT SIGNALS Data (07-00) Bus, Pins 1-8: This bus is comprised of eight TRI-STATE input/output lines. The bus provides bidirectional communications between the UART and the CPU. Data, control words, and status information are transferred via the 07-00 Data Bus. Serial Output (SOUn, Pin 11: This is the composite serial data output to the communications link (peripheral, MODEM or data set). The SOUT signal is set to the Marking (logic 1) state upon a Master Reset operation or when the transmitter is idle. External Clock Input/Output (XIN, XOUT) Pins 16 and 17: These two pins connect the main timing reference (crystal or signal clock) to the UART. When a crystal oscillator or a clock signal is provided, it drives the UART via XIN (see typical oscillator network illustration). PCC Package "~7NcV\C1W .. . 3811iili D,- 2 "r-~ D2- 3 31 t- DCD /65432 1 4443424140 D3- , 37 -~ DO 7 " .R D,- 5 3' -CTS D,- , 35 -MR D7 , ., iifR D&- 1 --- 3' -1IiITi RCLK 10 36 RfI Dl- 8 33 SIN 3511l1i'1 -~ Ne 12 " HS1845D RC'K- , 32 -RTS 34 NC INS8250A SOUT 13 33 INTR S'N- ID 31 r-1IlIT2 CSO 14 SDUT- " " NC .. 3D I-'NTR cal 15 31 AD CSO- 12 29 t-NC CS2 18 ., AI CSI- 13 28 t-AD iMiDDIif 17 IS AI m- " 2l t-AI BJmillilii'- 15 26 -A2 X1N- 16 25 -ADS 1819202122232425262728 xw ::~I j l:'~ ~D\~~m XDUT- 11 2. -CSDUT R- IB 23 -DOIS WR- I, 22 -RD TL/C/9329-18 vss- 2D 21 rill! Top View Top View Order Number INS8250N, INS8250N-B or INS8250N/ A + See NS Package Number N40A TL/C/9329-11 TABLE I. UART Reset Functions Order Number INS8250V-B See NS Package Number V44A Register/Signal Reset Control Reset State Interrupt Enable Register Master Reset 0000 0000 (Note 1) Interrupt Identification Register Master Reset 00000001 Line Control Register Master Reset 00000000 MODEM Control Register Master Reset 00000000 Line Status Register Master Reset 01100000 MODEM Status Register Master Reset XXXX 0000 (Note 2) SOUT Master Reset High INTR (RCVR Errs) Read LSR/MR Low INTR (RCVR Data Ready) Read RBR/MR Low INTR(THRE) Read IIR/Write THR/MR Low INTR (Modem Status Changes) Read MSR/MR Low OUT2 Master Reset High RTS Master Reset High DTR Master Reset High OUT 1 Master Reset High Note 1: Underlined bits are permanently low. Note 2: Bits 7-4 are driven by the input Signals. 4-12
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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Page 386 and 387: 00044 F90a :J- 226 Z • 227 MOVE A
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Page 390 and 391: Section 3 ISDN Components
Page 392 and 393: Introduction To National Semiconduc
Page 394 and 395: NSC Solutions for Layers 2 and 3 Na
Page 396 and 397: NSC Solutions: Systems Level Basic
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Page 400 and 401: ~National ~ Semiconductor PRELIMINA
Page 402 and 403: ISDN DEFINITIONS "B" Channel, or DS
Page 404: ~ '" TE2 UP TO 8 TERMINALS -
Page 407 and 408: Section 4 Contents INS8250/INS8250-
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Page 411 and 412: 3.0 AC Electrical Characteristics T
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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