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~National ~ Semiconductor DS96172/~A96172,DS96174/~A96174 Quad Differential Line Drivers General Description The DS96172/,..,A96172 and DS96174/,..,A96174 are high speed quad differential line drivers designed to meet EIA Standard RS-485. The devices have TRI-STATE® outputs and are optimized for balanced multipoint data bus transmission at rates up to 10 Mbps. The drivers have wide positive and negative common mode range for multipoint applications in noisy environments. Positive and negative current-limiting is provided which protects the drivers from line fault conditions over a + 12V to - 7.0V common mode range. A thermal shutdown feature is also provided and occurs at junction temperature of approximately 160·C. The DS96172/,..,A96172 features an active high and active low Enable, common to all four drivers. The DS96172/,..,A96174 features separate active high Enables for each driver pair. Compatible RS-485 receivers, transceivers, and repeaters are also offered to provide optimum bus performance. The respective device types are DS96173/,..,A96173, DS961751 ,..,A96175, DS96176/,..,A96176, DS96177 1 ,..,A96177 and DS96178/,..,A96178. Features • Meets EIA Standard RS-485 and RS-422A • Monotonic differential output switching • Transmission rate to 10 Mbs • TRI-STATE outputs • Designed for multipoint bus transmission • Common mode output voltage range: - 7V to + 12V • Operates from Single + 5V supply • Thermal shutdown protection • DS96172/,..,A96172/DS96174/,..,A96174 are lead and function compatible with the SN75172175174 or the AM26LS31/MC3487 respectively Connection Diagrams 16-Lead DIP DS96172/,..,A96172 DS96174/,..,A96174 lA 16 Vee lA 16 Vee lY 2 15 4A lY 2 1Z 14 4y lZ 3 13 4Z El,2 4 2Z 12 E 2Z 5 2Y 11 3Z 2Y 6 2A 10 3y 2A 7 GND 8 9 3A GND 8 Top View TLlF/9626-1 Top View Order Number DS96172DC/,..,A96172DC or DS96174DC/,..,A96174DC See NS Package Number J16A Order Number DS96172PC/,..,A96172PC or DS96174PC/,..,A96174PC See NS Package Number M16S TL/F/9626-2 6-27
..... .,... II) co en « :::l.. ...... II) ..... .,... co en (J) C ...... C') ..... .,... co en « :::l.. ...... C') ..... .,... co en (J) C ~National ~ Semiconductor DS96173/~A96173/DS96175/~A96175 Quad Differential Line Receivers General Description The DS96173/",A96173 and DS96175/",A96175 are high speed quad differential line receivers designed to meet EIA Standard RS-485. The devices have TRI-STATE outputs and are optimized for balanced multipoint data bus transmission at rates up to 10 Mbps. The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode input voltage range of -12V to + 12V. The receivers are therefore suitable for multipoint applications in noisy environments. The DS96173/",A96173 features an active high and active low Enable, common to all four receivers. The DS96175/",A96175 features separate active high Enables for each receiver pair. Compatible RS-485 drivers, transceivers, and repeaters are also offered to provide optimum bus performance. The respective device types are DS96172/29174, ",A96172/96174, DS96176, ",96176 and DS96177/96178,,,,A96177/96178. Features • Meets EIA Standard RS-485, RS-422A, RS-423A • Designed for multipoint bus applications • TRI-STATE Outputs • Common mode input voltage range: -12V to + 12V • Operates from single + 5V supply • Input sensitivity of ± 200 mV over common mode range • Input hysteresis of 50 mV typical • High input impedance • Fail-safe input/output features drive output HIGH when input is open • DS96173/",A96173/DS96175/",A96175 are lead and function compatible with SN75173/75175 or the AM26LS32/MC3486 respectively. Connection Diagrams 16-Lead DIP DS96173/",A96173 16-Lead DIP DS96175/",A96175 18 16 Vee 1A 2 15 48 1Y 144A 4 13 4y 2Y 5 12 E 2A 11 3Y 28 7 10 3A GND 9 38 18--'-11----. 1A 2 1Y 3 E1, 2...:..4 t--l>-i 2Y 5 2A 28 7 GND 8 16 Vee 15 48 144A 13 4y +-
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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m . r------------------------------
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
Page 545 and 546: Absolute Maximum Ratings* If Milita
Page 547 and 548: Electrical Characteristics unless o
Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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Page 561 and 562: .,... U) Z 3020 LPRINT USING" 1111
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Page 565 and 566: . II) or- II) Z
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Page 570 and 571: Section 6 Transmission Line Drivers
Page 572 and 573: ~National ~ Semiconductor Transmiss
Page 574 and 575: ~National ~ Semiconductor OS 1488 Q
Page 576 and 577: J?'A National ~ Semiconductor OS 14
Page 578 and 579: ~National ~ Semiconductor DS26C31 C
Page 580 and 581: ~National ~ Semiconductor DS26C32C
Page 582 and 583: ~National ~ Semiconductor DS34C86 Q
Page 584 and 585: ~National ~ Semiconductor PRELIMINA
Page 586 and 587: ~National ~ Semiconductor DS1692/DS
Page 588 and 589: ~National ~ Semiconductor DS75150 D
Page 590 and 591: ~National ~ Semiconductor DS75176A/
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Page 594 and 595: ~National ~ Semiconductor DS8922/22
Page 598 and 599: ~National ~ Semiconductor DS961771
Page 600 and 601: ~National ~ Semiconductor DS9637 AI
Page 602 and 603: • I .----------------------------
Page 604 and 605: Section 7 Physical Dimensions
Page 606 and 607: ~National ~ Semiconductor All dimen
Page 608 and 609: NS Package N16A N16A(REV E) 0.092 X
Page 610 and 611: t-------------I:..':::~"':I'-------
Page 612 and 613: 0.11M-0.118 (2.642-2.9971 .. ••
Page 614 and 615: NOTES
Page 616 and 617: ~National ~ Semiconductor Bookshelf
Page 618 and 619: RELIABILITY HANDBOOK-1986 Reliabili
Page 620 and 621: NATIONAL SEMICONDUCTOR CORPORATION
Page 622 and 623: NATIONAL SEMICONDUCTOR CORPORATION
Page 624: ~ National ~ Semiconductor
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