~ National ~ Semiconductor - Al Kossow's Bitsavers

-------------------------------------------------------------'c
~National
~ Semiconductor
PRELIMINARY
DP8344A Biphase Communications Processor-BCP
General Description
The DP8344A BCP is a communications processor designed
to efficiently process IBM 3270, 3299 and 5250 communications
protocol, a general purpose 8-bit protocol is
also supported.
The BCP integrates a 20 MHz 8-bit Harvard architecture
RISC processor, and an intelligent, software-configurable
transceiver on the same low power microCMOS chip. The
transceiver is capable of operating without significant processor
interaction, releasing processor power for other tasks.
Fast and flexible interrupt and subroutine capabilities with
on-chip stacks, make this power readily available.
The transceiver is mapped into the processor's register
space, communicating with the processor via an asynchronous
interface which enables both sections of the chip to
run from different clock sources. The transmitter and receiver
run at the same basic clock frequency although the receiver
extracts a clock from the incoming data stream to
ensure timing accuracy.
The BCP is designed to stand alone and is capable of implementing
a complete communications interface, using the
processor's spare power to control the complete system.
Alternatively, the BCP can be interfaced to another processor
with an on-chip interface controller arbitrating access to
data memory. Access to program memory is also possible,
providing the ability to download BCP code.
A simple line interface connects the BCP to the communications
line. The receiver includes an on-chip analog comparator,
suitable for use in a transformer-coupled environment,
although a TTL-level serial input is also provided for applications
where an external comparator is preferred.
A typical system is shown below. Both coax and twinax line
interfaces are shown, as well as an example of the (optional)
remote processor interface.
Table of Contents
1.0 Block Diagram
2.0 Connection Diagram
3.0 Pin Descriptions
4.0 Electrical Specifications
5.0 InstrucUon Set Overview
6.0 Instruction Set Reference
7.0 CPU Register
8.0 Remote Interface" Arbitration System
9.0 Remote Interface Reference
10.0 Transceiver
Features
Transceiver
• Software configurable for 3270, 3299, 5250 and general
8-bit protocols
• Fully registered status and control
• On-Chip analog line receiver
Processor
• 20 MHz clock (50 ns T-states)
• Max. instruction cycle: 200 ns
• 33 instruction types (50 total opcodes)
• ALU and barrel shifter
• 64k x 8 data memory address range
• 64k x 16 program memory address range
(note: typical system requires