~ National ~ Semiconductor - Al Kossow's Bitsavers

7.0 CPU Registers (Continued)
BIT DEFINITION TABLE
The following tables describe the location and function of all control and status bits in the various BCP addressable special
function registers. The Remote Interface Configuration register (RICI, which is addressable only by a remote system, is not
included.
CPU (for further information see Chapter on the CPU).
Bit Name Location Reset State Function
Timing CCS CPU Clock Select OCR [7] 1 Selects CPU clock frequency.
Control
CCS CPUCLK
0 OCLK
1 OCLK/2
Where OCLK is the frequency of the on-chip oscillator, or
the externally applied clock on input X1.
DW2-0 Data Memory OCR [2-0] 111 Selects from 0 to 7 wait states for accessing data memory.
Wait-State Select
IW1,0 Instruction Memory OCR [4,3] 11 Selects from 0 to 3 wait states for accessing instruction
Wait-State Select
memory.
COD Clock Out Disable ACR [2] 0 When high, CLK-OUT is at TRI-STATE.
Remote LOR' Lock Out Remote ACR [1] 0 When high, a remote processor is prevented from accessing
Interface
the BCP or its memory.
RR' Remote Read CCR[S] 0 Set whenever REM-RD is asserted. Cleared by writing a 1 to
[RR].
RW' Remote Write CCR[5] 0 Set whenever REM-WR is asserted. Cleared by writing a 1 to
[RW].
Interrupt BIC Bi-Directional ACR[4] 0 Controls the direction of BIRO.
Control
Interrupt Control
BIC BIRQ
0 Input
1 Output
BIRO Bi-Directional CCR[4] [Read Only]. Reflects the logic level of the (BIRO) input.
Interrupt ReOuest
Updated at the beginning of each instruction cycle.
GIE Global Interrupt ACR[O] 0 When low, disables all maskable interrupts. When high,
Enable
works with [IM4-0] to enable maskable interrupts.
IM4-0 Interrupt Mask ICR [4-0] 11111 Each bit, when set high, masks an interrupt.
Select IM4-0 Interrupt Priority
00000 No Mask -
XXXX1 Receiver 1 High
XXX1X Transmitter 2 t
XX1XX Line Turn-Around 3
X1XXX Bi-Directional 4 !-
1XXXX Timer 5 Low
1M3 functions as an interrupt mask only when BIRO is
defined as an input. When defined as an output, 1M3 controls
the state of BIRO.
'These bits represent \he only visibility and controllhatthe processor has into the operation of the remote Interface controiler. The Remote Interfece Configuration
regiater, {RICI, accessible only by a remote processor, provides further control functions. See Remote Interface Chapter for more information.
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