~ National ~ Semiconductor - Al Kossow's Bitsavers

~r-----------------------------------------------------~
~
~
C')
ClC)
11.
C
8.0 Remote Interface and Arbitration System (Continued)
IA~ ____________________________ ~I
IMEM
BCP
DMEM
REMOTE
PROCESSOR
ADDR t---------------......J
RA15-0
8
DATA \r=--:---------------------....J
RD7-0
The BCP Remote Arbitrator State Machine (RASM) must
know what hardware interfaces to the RP in order to time
the remote accesses correctly. To accomplish this, three
Interface Mode bits in {RIC 1 are used to define the hardware
interface. These bits are the Latched Write bit [LW],
the Latched Read bit [LR] and the Fast Buffered Write bit
[FBW].
7 6 5 4 3 2 o
IBIS I SS @il§JiiJ ST I MSI I MSO I
Interface Mode Bits
O-Buffered Read
I-Latched Read
o 0 -Slow Buffered Write
1 0 -Fast Buffered Write
X O-Latched Write
FIGURE 24. Minimum BCP/Remote Processor Interface
All combinations of Remote Reads or Writes with buffers or
latches can be configured via the Interface Mode bits. A
Buffered Read is accomplished by using a buffer for block D
and setting [LR] = O. Conversely, using a latch for block D
and setting [LR] = 1 configures the RASM for Latched
Reads. Using buffers for blocks A, B, and C and setting
[LW] = 0 allows either a Slow or Fast Buffered Write. Setting
[FBW] = 0 configures RASM for a Slow Buffered Write
and [FBW] = 1 designates a Fast Buffered Write. A
Latched Write is accomplished by using latches for blocks
A, B, and C and setting [LW] = 1.
EXECUTION CONTROL
TLIF/9336-96
The BCP can be started and stopped in two ways. I! the
BCP is not interfaced to another processor, it can be started
by pulsing RESET low while both REM-RD and REM-WR
are low. Execution then begins at location zero. If there is a
Remote Processor interfaced to the BCP, a write to {RIC 1
which sets the start bit [STRT] high will begin execution at
the current PC location. Writing a zero to [STRT] stops execution
after the current instruction is completed. A Single­
Step is accomplished by writing a one to the Single-Step bit
[SS] in {RIC l. This will execute the instruction at the current
PC, increment the PC, and then return to idle. [SS] returns
low after the single-stepped instruction has completed.
Two pins (WAIT and LOCK) and one register bit [LOR] can
also affect the BCP CPU or RIAS execution. I! WAIT is taken
low the required set-up time before the last read or write
T-state (before T 2), the read or write cycle will be extended
until WAIT is removed. LOCK prevents local accesses of
Data Memory. I! LOCK is asserted a hal! T-state before T 1,
further local accesses will be prevented by waiting the Timing
Control Unit. [LOR] prevents remote accesses when asserted.
The Timing Control Unit (TCU) is the BCP CPU sub
system responsible for timing each instruction. Once [LOR],
located in {ACR l. is set high, further remote accesses are
suspended.
Though the BCP runs independently of R lAS there is some
interaction between the two systems. [LOR] is one such
2-150