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~ National ~ Semiconductor - Al Kossow's Bitsavers

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8.0 Packet Transmission (Continued)<br />

TRANSMIT PACKET ASSEMBLY<br />

The NIC requires a contiguous assembled packet with the<br />

format shown. The transmit byte count includes the Destination<br />

Address, Source Address, length Field and Data. It<br />

does not include preamble and CRC. When transmitting<br />

data smaller than 46 bytes, the packet must be padded to a<br />

minimum size of 64 bytes. The programmer is responsible<br />

for adding and stripping pad bytes.<br />

TX BYTE COUNT<br />

(TBCRO.! )<br />

TRANSMISSION<br />

General Transmit Packet Format<br />

DESTINATION ADDRESS<br />

SOURCE ADDRESS<br />

TYPE LENGTH<br />

DATA<br />

-----------------<br />

PAD (IF DATA < 46 BYTES)<br />

6 BYTES<br />

6 BYTES<br />

2 BYTES<br />

~ 46 BYTES<br />

TL/F/8582-58<br />

Prior to transmission, the TPSR (Transmit Page Start Register)<br />

and TBCRO, TBCR 1 (Transmit Byte Count Registers)<br />

must be initialized. To initiate transmission of the packet the<br />

TXP bit in the Command Register is set. The Transmit<br />

Status Register (TSR) is cleared and the NIC begins to prefetch<br />

transmit data from memory (unless the NIC is currently<br />

receiving). If the interframe gap has timed out the NIC will<br />

begin transmission.<br />

CONDITIONS REQUIRED TO BEGIN TRANSMISSION<br />

In order to transmit a packet, the following three conditions<br />

must be met:<br />

1. The Interframe Gap Timer has timed out the first 6.4 J.Ls<br />

of the Interframe Gap (See appendix for Interframe Gap<br />

Flowchart)<br />

2. At least one byte has entered the FIFO. (This indicates<br />

that the burst transfer has been started)<br />

3. If the NIC had collided, the backoff timer has expired.<br />

In typical systems the NIC has already prefetchedthe first<br />

burst of bytes before the 6.4 J.Ls timer expires. The time<br />

during which NIC transmits preamble can also be used to<br />

load the FIFO.<br />

Note: If carrier sense is asserted before a byte has been loaded into the<br />

FIFO, the NIC will become a receiver.<br />

COLLISION RECOVERY<br />

During transmission, the Buffer Management logic monitors<br />

the transmit circuitry to determine if a collision has occurred.<br />

If a collision is detected, the Buffer Management logic will<br />

reset the FIFO and restore the Transmit DMA pOinters for<br />

retransmission of the packet. The COL bit will be set in the<br />

TSR and the NCR (Number of Collisions Register) will be<br />

incremented. If 15 retransmissions each result in a collision<br />

the transmission will be aborted and the ABT bit in the TSR<br />

will be set.<br />

Note: NCR reads as zeroes if excessive collisions are encountered.<br />

TRANSMIT PACKET ASSEMBLY FORMAT<br />

The following diagrams describe the format for how packets<br />

must be assembled prior to transmission for different byte<br />

ordering schemes. The various formats are selected in the<br />

Data Configuration Register.<br />

D15 D8 D7 DO<br />

DAI<br />

DA3<br />

DA5<br />

S<strong>Al</strong><br />

SA3<br />

SA5<br />

TIll<br />

DAO<br />

DA2<br />

DA4<br />

DAO<br />

DA2<br />

DA4<br />

T/lO<br />

DATA 1 DATA 0<br />

BOS ~ o. WTS ~ 1 in Data Configuration Register.<br />

This format is used with Series 32000, 808X type processors.<br />

D15 D8 D7 DO<br />

DAO<br />

DA2<br />

DA4<br />

SAO<br />

SA2<br />

SA4<br />

T/lO<br />

DAI<br />

DA3<br />

DA5<br />

S<strong>Al</strong><br />

SA3<br />

SA5<br />

TIll<br />

DATA 0 DATA 1<br />

BOS ~ 1, WTS ~ 1 in Data Configuration Register.<br />

This format is used with 68000 type processors.<br />

D7<br />

DAO<br />

DAI<br />

DA2<br />

DA3<br />

DA4<br />

DA5<br />

SAO<br />

S<strong>Al</strong><br />

SA2<br />

SA3<br />

BOS ~ 0, WTS ~ 0 in Data Configuration Register.<br />

This format is used with general 8-bit CPUS.<br />

Note: <strong>Al</strong>l examples above will result in a transmission of a packet in order of<br />

DAO, DA 1, DA2, DA3 ... bits within each byte will be transmitted least<br />

significant bit first.<br />

DA = Destination Address<br />

SA ~ Source Address<br />

T /L ~ Type/Length Field<br />

DO<br />

C<br />

."<br />

C»<br />

~ .....<br />

Z<br />

CJ)<br />

Co)<br />

N<br />

,co.<br />

CD<br />

C)<br />

o<br />

1-13

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