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~ National ~ Semiconductor - Al Kossow's Bitsavers

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-----------------------------------------------------------------------,c<br />

"a<br />

6.0 Instruction Set Reference (Continued)<br />

XOR<br />

Exclusive OR Immediate<br />

Syntax<br />

XOR n, rsd -immediate, limited register<br />

Affected Flags<br />

N,Z<br />

Description<br />

Logically exclusive ORs the immediate value n to the register<br />

rsd and places the result back into the register rsd. Note<br />

that only the active registers RO-R15 may be specified for<br />

rsd. The value of n is 8 bits wide.<br />

Example<br />

Encode/decode a data byte in register 20.<br />

XOR code-pattern, R20 ;encode/decode<br />

Instruction Format<br />

1 0 11 1 1 1 0 I<br />

. Opcode .<br />

15 11<br />

T-states<br />

2<br />

Bus Timing<br />

Figure 7<br />

Operation<br />

rsd XOR n -<br />

rsd<br />

n<br />

rsd<br />

3 0<br />

XORA Exclusive OR with Accumulator<br />

Syntax<br />

XORA Rs, Rd<br />

XORA Rs, [mlr]<br />

-register, register<br />

-register, indexed<br />

Affected Flags<br />

N,Z<br />

Description<br />

Logically exclusive ORs the source register Rs to the active<br />

accumulator and places the result into the destination specified.<br />

The destination may be either a register, Rd, or data<br />

memory via an index register mode, [mlr]. Note that register<br />

bank selection determines which accumulator is active.<br />

Example<br />

Decode the data byte just received and place it into data<br />

memory. This example assumes that the accumulator contains<br />

the "key" and that the index register IY points to the<br />

location where the information should be stored.<br />

EXX 1,1 ;select alternate banks<br />

XORA<br />

Instruction Format<br />

XORA Rs, Rd<br />

RTR, [IY + ] ;decode received byte and<br />

; save it<br />

15 9<br />

XORA Rs, [Mlr]<br />

1<br />

Rd<br />

15 8 6 4<br />

T-states<br />

XORA Rs, Rd -2<br />

XORA Rs, [mlr] -3<br />

00 - post-decrement<br />

01 - no change<br />

10 - post Increment<br />

11 - pre-Increment<br />

Bus Timing<br />

XORA Rs, Rd -Figure 7<br />

XORA Rs, [mlr] -Figure 12<br />

Operation<br />

XORA Rs, Rd<br />

Rs XOR accumulator -<br />

XORA Rs, [mlr]<br />

Rs XOR accumulator -<br />

Rd<br />

data memory<br />

4<br />

1 1<br />

Rs<br />

i i<br />

R.<br />

~<br />

00 -IW<br />

01 - IX<br />

10 - IY<br />

11 - IZ<br />

o<br />

o<br />

TL/F/9336-16<br />

co<br />

W<br />

...<br />

;<br />

2-123

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