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# #*************************** 16550A INITIALIZATION ***************************** movb movb movb movb movb movb $Ox080,lcr $4,txd $O,ler $Ox003,lcr $O,ler $OxOc7,fcr # #Set dlab = 1 for dlvlsor latch access #Low divisor latch 56k w/8.0 xtal tUpper dlvisor latch tDlab = 0, 8 bits, no parity, 1 stop #Disable UART interrupts #Fifo=> trigger = 14, reset & enable #**************************** INITIALIZE • 32202 (ICU) *************************** movd movb $1cu addr,rO $OxCa,lCu_mctl(rO) # # #RO = icu address #Set mode 8 blt bus mode, • # freeze counters, disable lnterrupts, # flxed prlorlty. movqb O,lcu cctl(rO) movqb -l,lcu lps(rO) movqb O,lCU csrc(rO) movqb O,lcu-csrc+aO(rO) movb $OxlO,lcu svct(rO) movqb -l,lcu elgt(rO) movqb -l,lcu-elgt+aO(rO) movqb $2,lcu-tpl(rO) movqb O,lcu tpl+aO(rO) movqb O,icu-fprt(rO) movqb 0,1cu-fprt+aO movqb 0,1cu-lsrv(rO) movqb 0,1cu-lsrv+aO(rO) movqb -l,iCU 1msk(rO) movqb -l,1cu-lmsk+aO(rO) #Halt the counters tSet all plns to interrupt source iNo cascaded lnterrupts (low reg) # (hlgh reg) #Set interrupt base vector #Set level triggering (low reg) #(hlgh reg) #Set high polarlty mode (low reg) #(hlgh reg) .Set highest priority to 0 (low reg) #(high reg) #Clear 1ntr in-servlce regs (low reg) #(high reg) #Mask all lntr (low reg) #(hlgh reg)H setcfg [1J - tEnable vectored intrp (1=1) movd $lCU addr,rO movb $OX02,lCU mctl(rO) movb $Ox010,iCU cctl(rO) movb $Oxfd,1cu tmsk(rO) movb $Oxff,lcu-lmsk+aO(rO) blspsrw $ (Ox800) # #Flxed mode, 8 bit bus mode #Set to internal sampling #Enable lrl #Mask all other lnterrupts #Enable cpu lntr's # #*************************** ENABLE 16550A INTERRUPTS ************************** movb $2,mcr •#Clear outl, out2 and enable rts endinit: movb $Ox07,ler #Enable all but modem status interrupts # #********************** ENDLESS LOOP WAITING FOR INTERRUPTS ******************** holdloop: nop br holdloop # # # # #****************************** INTERRUPT HANDLER ****************************** lsr: # save [rO,rl,r2,r3,r4,r5,r6,r7J movb iir,rO #RO- contains ilr cmpb rO,$OxOc6 i beq Isint iLine status lnterrupt cmpb rO,$OxOc4 # beq rdal #Recelver lnterrupt cmpb rO,$OxOcc # TL/C/9313-22 --! 4-81
eq rtmout cmpb rO, $OxOc2 beq threi cmpb rO,$OxOcO beq mS1nt 'Rec timeout lnterrupt # #THRE lnterrupt I iModem status interrupt i #************************** INVALID INTERRUPT • ROUTINE ************************** save [rO,rl,r2,r3] movd $4,rO addr message2,rl movd $2l,r2 movd $O,r3 svc restore [rO,rl,r2,r3] jump stop *# # i I i # i i II #Restore all reglsters t #********************* RECEIVER TIMEOUT * INTERRUPT ROUTINE ********************** # rtmout: jump rdal , #*************************** RECEIVER INTERRUPT ROUTINE ************************ t 'Thls portlon of the program ls reached when the recelved data available #interrupt is act1ve. Once in this routine each byte removed from the FIFO '1S placed in the deslgnated static base memory location (labelled rbuf). tThe data ready bit (DR) ln the LSR is checked before each byte ls removed ifrom the FIFO. Data sent will be compared to known data ln another designated tstatic base area (labelled Cbuf) by calling the compare subroutine. t rdai: movb $O,mer tOlsable RTS; stop transmlsslon addr rbuf(sb),r4 #r4 conta1ns rbuf base address movd rbufoff,r6 #Put rbuf offset runner lnto r6 rdrbr: movb rxd,O(r4)[r6:b] iStore a byte ln the receive buffer empb $Oxtf,O(r4)[r6:b] tIs it the last character addqw 1,r6 tIncrement offset ptr. addqw l,rbufoff iTrack r6 bne eont1nue i movw $O,r6 IReset polnter offset ,movw $O,rbufoff iReset rbufoff eont1nue: movb lsr,r3 tRead lsr andb $Ol,r3 iMask all but bit 0 cmpb $Ol,r3 i beq rdrbr #Read rbr agaln lf set movd r6,rbufoff #Put result of r6 back into rbufoff bsr compare # movb $2,mer Unable rts jump popall II i #****************************** TRANSMIT ROUTINE ******************************* i IThe transmitter sends data prev10usly loaded into the stat~c base memory area ilabelled sbuf. Thids routine sends data as 16 blocks of 16 bytes and 1 block #of 15 bytes, continuously. NOTE: Before each block transm1ssion occurs ICTS 11S cheeked to ensure that the reeeiver ready. i TL/C/9313-23 4·82
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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.----------------------------------
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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~~L ~------------------------------
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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N r--------------------------------
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~ ..,. r---------------------------
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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) r--------------------------------
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Absolute Maximum Ratings (Note 1) I
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(W) r------------------------------
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M r--------------------------------
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MUX~ __________________ The BIPLAN
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U) ,-------------------------------
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~r---------------------------------
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~ .--------------------------------
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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~L ______________ ___ ~ ~ 4.0 Elect
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ ,--------------------------------
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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.----------------------------------
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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-----------------------------------
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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,----------------------------------
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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-----------------------------------
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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m . r------------------------------
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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m r--------------------------------
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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Page 438 and 439: 8.0 Registers (Continued) Table II
Page 440 and 441: 9.0 Typical Applications (Continued
Page 442 and 443: Table of Contents 1.0 ABSOLUTE MAXI
Page 444 and 445: 3.0 AC Electrical Characteristics T
Page 446 and 447: 4.0 Timing Waveforms (Continued) Wr
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Page 450 and 451: 5.0 Block Diagram AO A, A2 CSD CSI
Page 452 and 453: 6.0 Pin Descriptions (Continued) tr
Page 454 and 455: ... .I>. '" Bit No. TABLE II. Summa
Page 456 and 457: 8.0 Registers (Continued) 8.3 PROGR
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Page 460 and 461: '" .j>. 01 PHil This shows the basi
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Page 464 and 465: 3. The Rx FIFO will hold 16 bytes r
Page 466 and 467: NS16550A E-J r-o ..... IRQ4 ICU CPU
Page 468 and 469: TITLE 550APP.ASM - NS16550A INITIAL
Page 470 and 471: 3.0 Board to Board Communications w
Page 472 and 473: DIAPPS.ASM Flow Chart l> z • ~ CO
Page 474 and 475: » z I "" CD RDAI: DISABLE IRTS, SE
Page 476 and 477: COMPARE: SET UP COMPARE BUffER POIN
Page 478 and 479: .set iCu imsk,lO *aO • set icu -c
Page 480 and 481: holdloop: nop # br hold loop # # #*
Page 482 and 483: # msint: save [rO,rl,r2,r3] # movd
Page 484 and 485: #3/30/B7••••• D2APPS.ASM
Page 488 and 489: -----------------------------------
Page 490 and 491: A Comparison of the I NS8250, NS 16
Page 492 and 493: -----------------------------------
Page 494 and 495: cessed (see Figure 4), The output o
Page 496 and 497: AC Electrical Characteristics T A =
Page 498 and 499: ~National ~ Semiconductor \ J micro
Page 500 and 501: 1.0 Absolute Maximum Ratings 2.0 Op
Page 502 and 503: 4.0 AC Electrical Characteristics (
Page 504 and 505: 5.0 Timing Waveforms (Continued) ii
Page 506 and 507: -----------------------------------
Page 508 and 509: 6.0 Connection Diagrams Dual-In-Lln
Page 510 and 511: 8.0 Block Diagram CPU INTERFACE INT
Page 512 and 513: 9.0 Registers (Continued) Bit three
Page 514 and 515: .----------------------------------
Page 516: -----------------------------------
Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
Page 521 and 522: Absolute Maximum Ratings (Notes 1 &
Page 523 and 524: fj ::z:: ~ :::IE :::IE ~ ,---------
Page 525 and 526: Applications Information (Continued
Page 527 and 528: Absolute Maximum Ratings (Notes 1 &
Page 529 and 530: Description of Pin Functions Pin No
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Page 533 and 534: ~ r--------------------------------
Page 535 and 536: Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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.... ~ ~ U) r----------------------
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..... U) z • U) r----------------
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~ .... ,---------------------------
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.,... U) Z 3020 LPRINT USING" 1111
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~ .... r---------------------------
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. II) or- II) Z
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,.. i ~~---------------------------
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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-----------------------------------
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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