~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics (Continued)
DMA Memory Read
I Tt I T2 I T3 I T4 I Tt I
BSCK
I- berl I-berh
ADSO
r'
drw
-+ asds I-
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MRD
ADO-7
(8. 16 BIT MODE)
AD8-15
(8 BIT MODE)
AD8-15
(1 6 BIT MODE)
-+ ds
..... dhl-
dsada-
AO-7 YIIIIIIII) D A AO-7XI I /
avrh
-+ rez I-
A8-15 A8-15
-+
A8-A15 YIIIIIIII) DATA -
d~
~h I-
AO-15X/I
I
TLIF19345-42
Symbol Parameter Min Max Units
berl Bus Clock to Read Strobe Low 43 ns
bcrh Bus Clock to Read Strobe High 40 ns
ds Data Setup to Read Strobe High 25 ns
dh Data Hold from Read Strobe High 0 ns
drw DMA Read Strobe Width Out 2*bcye - 15 ns
raz
Memory Read High to Address TRI-STATE
(Notes 1. 2)
beh + 40
asds Address Strobe to Data Strobe bel + 10 ns
dsada Data Strobe to Address Active bcyc - 10 ns
avrh Address Valid to Read Strobe High 3*bcye - 15 ns
Note 1: During a burst A8-A15 are not TRI-STATE if byte wide transfers are selected. On the last transfer A8-A15 are TRI-STATE as shown above.
Note 2: These limits include the RC delay inherent in our test method. These signals typically turn off within bch + 15 ns, enabling other devices to drive these
lines with no contention.
ns
1-93