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Functional Description Figure 1 is a block diagram of the JJ-AV22. TRANSMITTER The transmitter consists of a QPSK modulator, a transmit buffer and scrambler, and a transmit filter and line driver. In the asynchronous mode, serial transmit data from the host enters the transmit buffer, which synchronizes the data to the internal 600 bps or 1200 bps clock. Data which is underspeed relative to 600 bps or 1200 bps periodically has the last stop bit sampled twice, resulting in an added stop bit. Similarly, overspeed input data periodically has unsampled-and therefore deleted-stop bits. The MODl and MOD2 pins choose 8, 9, 10 or 11 bit character lengths. In synchronous mode the transmit buffer is disabled. The transmitter clock may be internal, external or derived from the recovered received data. A scrambler preceeds the encoder to ensure that the line spectrum is sufficiently distributed to avoid interference with the in-band supervisory single-frequency signaling system employed in most telephone system toll trunks. The randomized spectrum also facilitates timing recovery in the receiver. The scrambler is characterized by the following recursive equation: Yi = Xi EEl Yi-14 EEl Yi-1? where Xi is the scrambler input bit at time i, Yi is the scrambler output bit at time i. and EEl denotes the XOR operation. V.22-type modems achieve full-duplex 1200 bps operation by encoding transmitted data by bit-pairs (dibits). The digits (symbols) are transmitted at 600 Baud (symbols/sec), thus halving both the apparent line data rate and the required signal bandwidth. This allows both transmit and receive channels to coexist in the limited bandwidth telephone channel. The four unique dibits thus obtained are gray-coded and differentially phase modulate either a 1200 Hz (Calling mode) or 2400 Hz (Answer mode) carrier. Each dibit is encoded as a phase change relative to the phase of the preceding signal dibit element: Dibit Phase Shift 00 +90' 01 0' 11 10 -90' 180' At the receiver, the dibits are decoded and the bits are reassembled in the correct sequence. The left-hand digit of the dibit is the one occurring first in the data stream as it enters the modulator after the scrambler. In the 600 bps lowspeed mode, only the 00 and 11 dibits are utilized, representing 0 and 1, respectively. Two programmable tone generators provide V.25 calling tone (1300 Hz), CCITT answer tone (2100 Hz), guard tones (550 Hz, 1800 Hz) and 16 DTMF tone pairs. The DTMF selection matrix is shown in Table III. The summed QPSK modulator and tone generator outputs drive a lowpass filter which both serves as a fixed compromise amplitude and delay equalizer for the telephone line and reduces output harmonic energy. The filter output drives an output buffer amplifier with low output impedance. The buffer provides a nominal 0.7 Vrms output in data mode. In the dialer mode, nominal DTMF output levels are 0.90 Vrms (low group) and 1.11 Vrms (high group). These levels are + 2 dB and + 4 dB with respect to data mode output level. RECEIVER The received signal from the line-connection circuitry drives a lowpass filter which performs anti-aliasing, and compromise amplitude and delay equalization of the incoming signal. Depending upon mode selection the following mixer either passes (Answer mode) or down converts (Calling mode) the signal to the 1200 Hz bandpass filter. In Analog Loopback mode, the receiver calling and answer mode assignments are inverted, which forces the receiver to operate in the transmitter frequency band. In this self-test configuration, a fraction of the transmit signal reflects to the RXIN pin due to the mismatch caused by the modem being on-hook (disconnected from the telephone line). In Data mode, the 1200 Hz bandpass filter passes the desired received signal while attenuating the adjacent transmitted signal component reflected from the line (talker echo). The chosen passband converts the spectrum of the received highspeed signal to a raised cosine shape to minimize intersymbol interference in the recovered data. Following the filter is a soft limiter and a signal energy detector. An external capacitor is required to eliminate the DC offset between the soft limiter output and the following limiter/comparator. The energy detector provides a digital indication that energy is present within the filter passband at a level above a preset threshold. At least 2 dB of hysteresis is provided between on and off levels to stabilize the detector output. In Dialer mode, integration times are modified so that the detector output follows the on/off envelope signature of call progress tones. The limiter output drives the QPSK demodulator and the carrier and clock recovery phase-locked loops; these form a digital coherent receiver. The demodulator outputs are inphase (I) and quadrature (Q) binary signals which together represent the recovered dibit stream. The dibit decoder circuit utilizes the recovered clock signal to convert this dibit stream to serial data at 600 bps or 1200 bps. The recovered bit stream is then descrambled, using the inverse of the transmit scrambler algorithm. In synchronous mode the descrambler output is identically the received data, while in asynchronous mode the descrambler output stream is selectively processed by the receive buffer. Underspeed data presented to the transmitting modem passes essentially unchanged through the receive buffer. Overspeed data, which had stop bits deleted at the transmitter, has those stop bits reinserted by the receive buffer. (Generally, stop bit lengths will be elastic.) The receive buffer output is then presented to the receive data pin (RXD) at a nominal intracharacter rate of 1219.05 bps in both basic and extended signaling rate modes. MASTER CLOCK/OSCILLATOR/DIVIDER CHAIN The JJ-AV22 clock source may be either a quartz crystal operating in parallel mode or an external signal source at 3.6864 MHz. The crystal is connected between XTL 1 and XTL2, with 30 pF net capacitance from each pin to ground (see Figure 1). The external capacitors should be mica or high-Q ceramic. An external circuit may be driven from XTL2: AC coupling to a high impedance load should be used; total capacitance to ground from XTL2, including the 5-21
IlAV22 RXIN LOCAL OSCILLATOR (L.O.) LIM 1 ~ EDEf RLST ." C :J 9- 0' :J !. c CD fI) () ... -0' .. 0' :J l' :::J g. I:: ~ ~ I\) EfC ~I Scr.4-r·----------------~ 14 6 1 ~ RXD TXD ~I 6 ~I 1 ~ TXO TEST HSKl HSK2 DOT MODl MOD2 SYNC TXSQ cIA HS AGND OOND YOO Yss SCRM FIGURE 1. Block Diagram TL1H/9415-2
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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Page 490 and 491: A Comparison of the I NS8250, NS 16
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Page 508 and 509: 6.0 Connection Diagrams Dual-In-Lln
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Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
Page 521 and 522: Absolute Maximum Ratings (Notes 1 &
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Page 525 and 526: Applications Information (Continued
Page 527 and 528: Absolute Maximum Ratings (Notes 1 &
Page 529 and 530: Description of Pin Functions Pin No
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Page 535 and 536: Electrical Characteristics Unless o
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Page 549 and 550: Functional Description* (Continued)
Page 551 and 552: ,...A212AT RECEIVE FILTER p--------
Page 553 and 554: TABLE III. Remote Digital Loopback
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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