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3.0 Pin Descriptions (Continued) Signal I/O Pin Reset State INSTRUCTION MEMORY INTERFACE (Continued) Instruction Address Bus: (Continued) IA9 0 64 0 16-bit Instruction memory Address bus. IA8 0 65 0 IA7 0 68 0 IA6 0 69 0 IA5 0 70 0 IA4 0 71 0 IA3 0 72 0 IA2 0 73 0 IA1 0 74 0 lAO (lSB) 0 75 0 Instruction Bus: 115 (MSB) 1/0 76 16-bit Instruction memory data bus. 114 1/0 77 113 1/0 78 112 1/0 79 111 1/0 80 110 1/0 81 19 1/0 82 18 1/0 83 17 1/0 2 16 1/0 3 15 1/0 4 14 1/0 5 13 1/0 6 12 1/0 7 11 1/0 8 10 (lSB) 1/0 9 Timing Control: Description IWR 0 56 I Instruction WRite. Instruction memory write strobe. IClK 0 51 0 Instruction CLocK. Delimits instruction fetch cycles. Rises during the first half of T1, signifying the start of an instruction cycle, and falls when the next instruction address is valid. DATA MEMORY INTERFACE Address Bus: A15(MSB) 0 10 0 High byte of 16-bit memory Address. A14 0 11 0 A13 0 12 0 A12 0 13 0 A11 0 14 0 A10 0 15 0 A9 0 16 0 A8 0 17 0 Multiplexed Address/Data Bus: AD7 1/0 18 0 low byte of 16-bit data memory Address, multiplexed with 8-bit Data bus. AD6 1/0 19 0 AD5 1/0 20 0 AD4 1/0 21 0 AD3 1/0 24 0 AD2 1/0 25 0 AD1 1/0 26 0 ADO (lSB) 1/0 27 0 2-65
3.0 Pin Descriptions (Continued) Signal I/O Pin Reset State DATA MEMORY INTERFACE (Continued) Timing/Control: Description ALE 0 28 0 Address latch Enable. Demultiplexes AD bus. Address should be latched on the falling edge. READ 0 29 I Data memory READ strobe. Data is latched on the rising edge. WRITE 0 30 I Data memory WRITE strobe. Data is presented on the rising edge. TRANSCEIVER INTERFACE DATA-IN I 39 X logic level serial DATA INput. <strong>Al</strong>G-IN+ I 42 X Non-inverting AnaloG INput for biphase serial data. <strong>Al</strong>G-IN- I 41 X Inverting AnaloG INput for biphase serial data. DATA-OUT 0 38 I Biphase serial DATA OUTput (inverted). DATA-DlY 0 37 0 Biphase serial DATA output DelaYed by one-quarter bit time. TX-ACT 0 36 0 Transmitter ACTive. Normally low, goes high to indicate serial data is being transmitted. Used to enable external line drive circuitry. REMOTE INTERFACE RAE I 46 X Remote Access Enable. A "chip-select" input to allow host access of BCP functions and memory. CMD I 45 X CoMmanD input. When high, remote accesses are directed to the Remote Interface Configuration (RIC l register. When low, remote accesses are directed to data-memory, instruction-memory or program counter as determined by (RICl. REM-RD I 47 X REMote ReaD. When active along with RAE, a remote read cycle is requested; serviced by the BCP when the data bus becomes available. REM-WR I 48 X REMote WRite. When active along with RAE, a remote write cycle is requested; serviced by the BCP when the data bus becomes available. XACK 0 50 I Transfer ACKnowledge. Normally high, goes low on REM-RD (or REM-WR going low if RAE low) and returns high when the transfer is complete. Normally used as a "wait" signal to the remote processor. WR-PEND 0 49 I WRite PENDing. In a system configuration where remote write cycles are latched, indicates when the latches contain valid data which is yet to be serviced by the BCP. lOCK I 44 X The remote processor uses this input to lOCK out local (BCP) accesses to datamemory. Once the remote processor has been granted the bus, lOCK gives it sole access to the bus and BCP accesses are "waited". lCl 0 31 0 loCal. Normally low goes high when the BCP relinquishes the data and address bus to service a Remote Access. EXTERNAL INTERRUPTS BIRQ I/O 53 I Bi-directionallnterrupt ReQuest. As an input, can be used as an active low interrupt input (maskable and level-sensitive). As an output, can be used to generate remote system interrupts, reset via (RIC l. NMI I 52 X Non-Maskable Interrupt. Negative edge sensitive interrupt input. 2-66
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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13.0 Bus Arbitration and Timing The
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15.0 Switching Characteristics AC S
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
Page 181 and 182: Detailed Functional Pin Description
Page 183 and 184: Message Format (Continued) DATA REC
Page 185 and 186: Timing Characteristics (Notes 2, 6,
Page 187 and 188: Timing Waveforms (Continued) 4T±(T
Page 189 and 190: Typical Applications (Continued) +5
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Page 195 and 196: Timing Characteristics (Continued)
Page 197 and 198: Functional Timing Waveforms (Contin
Page 199 and 200: Typical Applications (Continued) DA
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Page 205 and 206: Absolute Maximum Ratings (Note 1) I
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Page 211 and 212: MUX~ __________________ The BIPLAN
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Page 219 and 220: An EPROM implementation was selecte
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Page 231: 2.0 Connection Diagram A13- 12 A12-
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6.0 Instruction Set Reference (Cont
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! 6.0 Instruction Set Reference (Co
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~ ~ 6.0 Instruction Set Reference (
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== ~ 6.0 Instruction Set Reference
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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~ Lt) o N co U) Z ::::: o Lt) '
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4.0 Timing Waveforms (Continued) Re
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6.0 Pin Descriptions (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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3.0 AC Electrical Characteristics T
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4.0 Timing Waveforms (Continued) Wr
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5.0 Block Diagram AO A, A2 CSD CSI
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6.0 Pin Descriptions (Continued) tr
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... .I>. '" Bit No. TABLE II. Summa
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) When the
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'" .j>. 01 PHil This shows the basi
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3. The Rx FIFO will hold 16 bytes r
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NS16550A E-J r-o ..... IRQ4 ICU CPU
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TITLE 550APP.ASM - NS16550A INITIAL
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3.0 Board to Board Communications w
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DIAPPS.ASM Flow Chart l> z • ~ CO
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» z I "" CD RDAI: DISABLE IRTS, SE
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COMPARE: SET UP COMPARE BUffER POIN
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.set iCu imsk,lO *aO • set icu -c
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holdloop: nop # br hold loop # # #*
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# msint: save [rO,rl,r2,r3] # movd
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#3/30/B7••••• D2APPS.ASM
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# #*************************** 1655
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A Comparison of the I NS8250, NS 16
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cessed (see Figure 4), The output o
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AC Electrical Characteristics T A =
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~National ~ Semiconductor \ J micro
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1.0 Absolute Maximum Ratings 2.0 Op
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4.0 AC Electrical Characteristics (
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5.0 Timing Waveforms (Continued) ii
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6.0 Connection Diagrams Dual-In-Lln
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8.0 Block Diagram CPU INTERFACE INT
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9.0 Registers (Continued) Bit three
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Section 5 Contents MM74HC942 300 Ba
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Absolute Maximum Ratings (Notes 1 &
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fj ::z:: ~ :::IE :::IE ~ ,---------
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Applications Information (Continued
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Absolute Maximum Ratings (Notes 1 &
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Description of Pin Functions Pin No
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Electrical Characteristics Unless o
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C'I 5 Pin Descriptions (Continued)
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IlAV22 RXIN LOCAL OSCILLATOR (L.O.)
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Functional Description (Continued)
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Functional Description (Continued)
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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.,... U) Z 3020 LPRINT USING" 1111
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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t-------------I:..':::~"':I'-------
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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~ National ~ Semiconductor
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