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10.0 Transceiver (Continued)
RA Interrupt
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060504030201 DO R
OA Interrupt
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LTA Interrupt
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LA - Line Active
t
t t t
RA - Receiver Active
LA OA, RA, LA
DAY - Data Available
Command
LTA
LTA - Line Tum Arcund
flags
TL/F/9336-46
FIGURE 41, Timing of Receiver Flags Relative to Incoming Data
clearing [RA] and asserting the Line Turn-Around flag,
[LTA] indicating that a message was received with no errors.
For the 3270 and 3299 protocols, [L TA] can be used
to initiate an immediate transmitter FIFO load; for the other
protocols, an appropriate response delay time may be needed.
[LTA] is cleared by loading the transmitter's FIFO, writing
a one to [LTA] in the Network Command flag register, or
by asserting [TRES].
Receiver Errors
If the Receiver Active flag, [RAJ. is asserted, the selected
receiver input source is continuously checked for errors,
which are reported to the CPU by asserting the receiver
Error flag, [RE], and setting the appropriate receiver error
flags in the Error Code Register [ECR). If a line condition
occurs which results in multiple errors being created, only
first error to be detected will be latched into [ECR). Once
an error has been detected and the appropriate error flag
has been set, the receiver is disabled, clearing [RA] and
preventing the Line Turn-Around flag and interrupt [L TA]
from being asserted. The Line Active flag [LA] remains asserted
if signal transitions continue to be detected on the
input.
5 error flags are provided in [ECR):
7 6 5 4 3 2 o
I rsv I rsv I rsv I OVF I PAR liES I LMBT I RDIS I
[OVF]
[PAR]
[lES]
Overflow Flag-Asserted when the decoder
writes to the first location of the FIFO while [RFF]
is asserted. The word in the first location will be
over-written; there will be no effect on the last two
locations.
Parity Error Flag-Asserted when a received
frame fails an even (word) parity check.
Invalid Ending Sequence Flag-Asserted during
an expected end sequence when an error occurs
in the mini code-violation. Not valid in 5250 modes.
[LMBTI Loss of Mid-Bit Transition-Asserted when the
expected biphase-encoded mid-bit transition does
not occur within the expected window. Indicates a
loss of receiver synchronization.
[RDIS] Receiver Disabled While Active-Asserted when
an active receiver is disabled by the transmitter being
activated.
To determine which error has occurred, the CPU must read
[ECR). This is accomplished by asserting the Select Error
Codes control bit, [SEC] and reading [RTR). The [ECR) is
only 5 bits wide, therefore the upper 3 bits are still the output
of the receive FIFO. See Figure 41. The act of reading
[ECR) resets the receiver to idle, in which case it again
monitors the incoming data stream for a new start sequence.
[SEC] control bit must be de-asserted to read the
FIFO's data from [RTR).
If data is present in the FIFO when the error occurs, the
Data Available flag [DAV] is de-asserted when the error is
detected, being re-asserted when [ECR) is read. Data present
in the FIFO before the error occurred is still available to
the CPU. The flexibility is provided, therefore, to read the
error type and still recover data loaded into the FIFO before
the error occurred. [TRES] the Transceiver Reset, can be
asserted at any time, clearing both Transceiver FIFOs and
the error flags.
Transceiver Interrupts
The transceiver has access to 3 CPU interrupt vectors, one
each for the transmitter and receiver, and a third, the Line
Turn-Around interrupt, providing a fast turn around capability
between receiver and transmitter. The receiver interrupt is
the highest priority interrupt (excluding NMI), followed by the
transmitter and Line Turn-Around interrupts, respectively.
The three interrupt vector addresses and a full description
of the interrupts are given in Table XXVII.
The receiver interrupt is user-selectable from 4 possible
sources (only 3 used at present) by specifying a 2-bit field,
the Receiver Interrupt Select bits [RIS1,O] in the Interrupt
Control Register [lCR). A full description is given in Table
XXVIII.
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