~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics (Continued)
DMA Address Generation
T1' (NOTE 1) T2' T3' T4' T1 T2 13
BSCK'--'r--'I'-J~~~
ADS 1
ADSO
r"' ~ beadz
- beh_ --bel ~ beye
beash - .~ beasl beash -
~ beasl
beadv
--=:j ads ~adh- aswo-r-t adh
~ beadv r--I+ ads +
ADO-15 A16-A31 AO-A15 DATA
TLlF/8582-81
Symbol Parameter Min Max Units
bcyc
Bus Clock Cycle Time
(Note 2)
50 1000 ns
bch Bus Clock High Time 22.5 ns
bcl Bus Clock Low Time 22.5 ns
bcash Bus Clock to Address Strobe High 34 ns
bcasl Bus Clock to Address Strobe Low 44 ns
aswo Address Strobe Width Out bch ns
bcadv Bus Clock to Address Valid 45 ns
bcadz
Bus Clock to Address TRI-STATE
(Note 3)
15 55
ads Address Setup to ADSO/l Low bch - 15 ns
adh Address Hold from ADSO/l Low bcl- 5 ns
Nole 1: Cycles T1', T2', T3', T4' are only issued for the first transfer in a burst when 32-bit mode has been selected.
Note 2: The rate of bus clock must be high enough to support transfers tolfrom the FIFO at a rate greater than the serial network transfers from/to the FIFO.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to drive these lines with
no contention.
ns
1-42